公开(公告)号：US20170170303A1

公开(公告)日：2017-06-15

申请号：US15375094

申请日：2016-12-11

Applicant: Microchip Technology Incorporated

Inventor： Jack Wong ,  Sajid Kabeer ,  Mel Hymas ,  Santosh Murali ,  Brad Kopp

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/788

CPC classification number: H01L29/66825 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02318 ,  H01L21/02323 ,  H01L21/02337 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/7881

Abstract: Methods of fabricating a memory cell of a semiconductor device, e.g., an EEPROM cell, having a sidewall oxide are disclosed. A memory cell structure may be formed including a floating gate and an ONO film over the conductive layer. A sidewall oxide may be formed on a side surface of the floating gate by a process including depositing a thin high temperature oxide (HTO) film on the side surface of the conductive layer, and performing a rapid thermal oxidation (RTO) anneal. The thin HTO film may be deposited before or after performing the RTO anneal. The sidewall oxide formation process may provide an improved memory cell as compared with known prior art techniques, e.g., in terms of endurance and data retention.

公开(公告)号：US20190097027A1

公开(公告)日：2019-03-28

申请号：US16110330

申请日：2018-08-23

Applicant: Microchip Technology Incorporated

Inventor： Mel Hymas ,  Bomy Chen ,  Greg Stom ,  James Walls

IPC: H01L29/66 ,  H01L29/788 ,  H01L21/3213 ,  H01L21/3105 ,  H01L21/265

Abstract: A method of forming a memory cell, e.g., flash memory cell, may include (a) depositing polysilicon over a substrate, (b) depositing a mask over the polysilicon, (c) etching an opening in the mask to expose a surface of the polysilicon, (d) growing a floating gate oxide at the exposed polysilicon surface, (e) depositing additional oxide above the floating gate oxide, such that the floating gate oxide and additional oxide collectively define an oxide cap, (f) removing mask material adjacent the oxide cap, (g) etching away portions of the polysilicon uncovered by the oxide cap, wherein a remaining portion of the polysilicon defines a floating gate, and (h) depositing a spacer layer over the oxide cap and floating gate. The spacer layer may includes a shielding region aligned over at least one upwardly-pointing tip region of the floating gate, which helps protect such tip region(s) from a subsequent source implant process.

公开(公告)号：US10700077B2

公开(公告)日：2020-06-30

申请号：US15921858

申请日：2018-03-15

Applicant: Microchip Technology Incorporated

Inventor： Mel Hymas ,  James Walls ,  Sonu Daryanani

IPC: H01L27/11517 ,  H01L27/105 ,  H01L21/28 ,  H01L29/788 ,  H01L29/423 ,  H01L29/66

Abstract: A memory cell, e.g., a flash memory cell, includes a substrate, a flat-topped floating gate formed over the substrate, and a flat-topped oxide region formed over the flat-topped floating gate. The flat-topped floating gate may have a sidewall with a generally concave shape that defines an acute angle at a top corner of the floating gate, which may improve a program or erase efficiency of the memory cell. The flat-topped floating gate and overlying oxide region may be formed with without a floating gate thermal oxidation that forms a conventional “football oxide.” A word line and a separate erase gate may be formed over the floating gate and oxide region. The erase gate may overlap the floating gate by a substantially greater distance than the word line overlaps the floating gate, which may allow the program and erase coupling to the floating gate to be optimized independently.

公开(公告)号：US20190207006A1

公开(公告)日：2019-07-04

申请号：US15922571

申请日：2018-03-15

Applicant: Microchip Technology Incorporated

Inventor： Mel Hymas ,  James Walls ,  Sonu Daryanani

IPC: H01L29/423 ,  H01L27/11521

CPC classification number: H01L29/42328 ,  G11C16/0408 ,  G11C16/08 ,  G11C16/14 ,  H01L27/11521 ,  H01L29/7841

Abstract: A memory cell, e.g., a flash memory cell, includes a substrate, a floating gate formed over the substrate, and a word line and an erase gate formed over the floating gate. The word line overlaps the floating gate by a first lateral overlap distance, and the erase gate overlaps the floating gate by a second lateral overlap distance that is substantially greater than the first lateral distance. This configuration allows the program and erase coupling to the floating gate to be optimized independently, e.g., to decrease or minimize the program current and/or increase or maximize the erase current for the cell.

公开(公告)号：US20140269102A1

公开(公告)日：2014-09-18

申请号：US14209275

申请日：2014-03-13

Applicant: Microchip Technology Incorporated

Inventor： Kent Hewitt ,  Jack Wong ,  Bomy Chen ,  Sonu Daryanani ,  Jeffrey A. Shields ,  Daniel Alvarez ,  Mel Hymas

IPC: G11C16/10

CPC classification number: G11C16/0416 ,  H01L29/42328 ,  H01L29/7881

Abstract: An electrically erasable programmable read only memory (EEPROM) cell may include a substrate including at least one active region, a floating gate adjacent the substrate, a write/erase gate defining a write/erase path for performing high voltage write and erase operations, and a read gate defining a read path for performing low voltage read operations, wherein the read path is distinct from the write/erase path. This allows for a smaller read gate oxide, thus allowing the cell size to be reduced. Further, the EEPROM cell may include two independently controllable read gates, thereby defining two independent transistors which allows better programming voltage isolation. This allows the memory array to be drawn using a common source instead of each column of EEPROM cells needing its own source line. This makes the array more scalable because the cell x-dimension would otherwise be limited by each column needing two metal 1 pitches.

Abstract translation: 电可擦除可编程只读存储器（EEPROM）单元可以包括：衬底，其包括至少一个有源区域，与衬底相邻的浮置栅极;限定用于执行高电压写入和擦除操作的写/擦除路径的写/擦除栅极;以及 限定用于执行低电压读取操作的读取路径的读取门，其中读取路径与写/擦除路径不同。 这允许更小的读栅极氧化物，从而允许电池尺寸减小。 此外，EEPROM单元可以包括两个可独立控制的读取门，从而限定两个独立的晶体管，其允许更好的编程电压隔离。 这允许使用公共源而不是需要其自己的源极线的每一列EEPROM单元来绘制存储器阵列。 这使得阵列更具可扩展性，因为单元格x维度否则将受到需要两个金属1间距的每列限制。

公开(公告)号：US10424589B2

公开(公告)日：2019-09-24

申请号：US15983461

申请日：2018-05-18

Applicant: Microchip Technology Incorporated

Inventor： James Walls ,  Mel Hymas ,  Sajid Kabeer

IPC: H01L21/225 ,  H01L21/266 ,  H01L21/28 ,  H01L27/11521 ,  H01L29/08 ,  H01L29/66 ,  H01L29/788

Abstract: A method is provided for forming an integrated circuit memory cell, e.g., flash memory cell. A pair of spaced-apart floating gate structures may be formed over a substrate. A non-conformal spacer layer may be formed over the structure, and may include spacer sidewall regions laterally adjacent the floating gate sidewalls. A source implant may be performed, e.g., via HVII, to define a source implant region in the substrate. The spacer sidewall region substantially prevents penetration of source implant material, such that the source implant region is self-aligned by the spacer sidewall region. The source implant material diffuses laterally to extend partially under the floating gate. Using the non-conformal spacer layer, including the spacer sidewall regions, may (a) protect the upper corner, or “tip” of the floating gate from rounding and (b) provide lateral control of the source junction edge location under each floating gate.

公开(公告)号：US10347728B1

公开(公告)日：2019-07-09

申请号：US15922571

申请日：2018-03-15

Applicant: Microchip Technology Incorporated

Inventor： Mel Hymas ,  James Walls ,  Sonu Daryanani

IPC: H01L29/00 ,  H01L29/423 ,  H01L27/11521 ,  G11C16/08 ,  G11C16/04 ,  G11C16/14 ,  H01L29/78

Abstract: A memory cell, e.g., a flash memory cell, includes a substrate, a floating gate formed over the substrate, and a word line and an erase gate formed over the floating gate. The word line overlaps the floating gate by a first lateral overlap distance, and the erase gate overlaps the floating gate by a second lateral overlap distance that is substantially greater than the first lateral distance. This configuration allows the program and erase coupling to the floating gate to be optimized independently, e.g., to decrease or minimize the program current and/or increase or maximize the erase current for the cell.

公开(公告)号：US10050131B2

公开(公告)日：2018-08-14

申请号：US15375094

申请日：2016-12-11

Applicant: Microchip Technology Incorporated

Inventor： Jack Wong ,  Sajid Kabeer ,  Mel Hymas ,  Santosh Murali ,  Brad Kopp

IPC: H01L29/66 ,  H01L29/788 ,  H01L21/02 ,  H01L29/423 ,  H01L21/28

Abstract: Methods of fabricating a memory cell of a semiconductor device, e.g., an EEPROM cell, having a sidewall oxide are disclosed. A memory cell structure may be formed including a floating gate and an ONO film over the conductive layer. A sidewall oxide may be formed on a side surface of the floating gate by a process including depositing a thin high temperature oxide (HTO) film on the side surface of the conductive layer, and performing a rapid thermal oxidation (RTO) anneal. The thin HTO film may be deposited before or after performing the RTO anneal. The sidewall oxide formation process may provide an improved memory cell as compared with known prior art techniques, e.g., in terms of endurance and data retention.

公开(公告)号：US09455037B2

公开(公告)日：2016-09-27

申请号：US14209275

申请日：2014-03-13

Applicant: Microchip Technology Incorporated

Inventor： Kent Hewitt ,  Jack Wong ,  Bomy Chen ,  Sonu Daryanani ,  Jeffrey A. Shields ,  Daniel Alvarez ,  Mel Hymas

IPC: G11C11/34 ,  G11C16/04 ,  H01L29/423 ,  H01L29/788

CPC classification number: G11C16/0416 ,  H01L29/42328 ,  H01L29/7881

Abstract: An electrically erasable programmable read only memory (EEPROM) cell may include a substrate including at least one active region, a floating gate adjacent the substrate, a write/erase gate defining a write/erase path for performing high voltage write and erase operations, and a read gate defining a read path for performing low voltage read operations, wherein the read path is distinct from the write/erase path. This allows for a smaller read gate oxide, thus allowing the cell size to be reduced. Further, the EEPROM cell may include two independently controllable read gates, thereby defining two independent transistors which allows better programming voltage isolation. This allows the memory array to be drawn using a common source instead of each column of EEPROM cells needing its own source line. This makes the array more scalable because the cell x-dimension would otherwise be limited by each column needing two metal 1 pitches.

Abstract translation: 电可擦除可编程只读存储器（EEPROM）单元可以包括：衬底，其包括至少一个有源区域，与衬底相邻的浮置栅极;限定用于执行高电压写入和擦除操作的写/擦除路径的写/擦除栅极;以及 限定用于执行低电压读取操作的读取路径的读取门，其中读取路径与写/擦除路径不同。 这允许更小的读栅极氧化物，从而允许电池尺寸减小。 此外，EEPROM单元可以包括两个可独立控制的读取门，从而限定两个独立的晶体管，其允许更好的编程电压隔离。 这允许使用公共源而不是需要其自己的源极线的每一列EEPROM单元来绘制存储器阵列。 这使得阵列更具可扩展性，因为单元格x维度否则将受到需要两个金属1间距的每列限制。

公开(公告)号：US10700171B2

公开(公告)日：2020-06-30

申请号：US15887088

申请日：2018-02-02

Applicant: Microchip Technology Incorporated

Inventor： Sonu Daryanani ,  Bomy Chen ,  Mel Hymas

IPC: H01L21/28 ,  H01L27/11521 ,  H01L29/423 ,  H01L29/788 ,  H01L29/06 ,  H01L29/66

Abstract: A method for manufacturing a flash memory device on a substrate may include: preparing the substrate with shallow trench isolation to define active sections; depositing a floating gate oxide layer on the prepared substrate; depositing a floating gate polysilicon layer on the floating gate oxide layer; polishing the floating gate polysilicon layer to isolate a plurality of floating gates above the active sections of the substrate; depositing a silicon nitride layer on top of the plurality of floating gates; patterning and etching the silicon nitride layer to create silicon nitride features; depositing a set of oxide spacers along sides of the silicon nitride features; implanting a source junction into the substrate beneath the individual floating gates; removing the floating gate polysilicon layer except where beneath individual oxide spacers, then removing the set of oxide spacers; depositing an inter-poly layer on top of the remaining floating gates; depositing a second polysilicon layer on top of the inter-poly layer; and patterning and etching the second polysilicon layer to separate the second polysilicon layer into word line devices and erase gates.