公开(公告)号：US10050131B2

公开(公告)日：2018-08-14

申请号：US15375094

申请日：2016-12-11

Applicant: Microchip Technology Incorporated

Inventor： Jack Wong ,  Sajid Kabeer ,  Mel Hymas ,  Santosh Murali ,  Brad Kopp

IPC: H01L29/66 ,  H01L29/788 ,  H01L21/02 ,  H01L29/423 ,  H01L21/28

Abstract: Methods of fabricating a memory cell of a semiconductor device, e.g., an EEPROM cell, having a sidewall oxide are disclosed. A memory cell structure may be formed including a floating gate and an ONO film over the conductive layer. A sidewall oxide may be formed on a side surface of the floating gate by a process including depositing a thin high temperature oxide (HTO) film on the side surface of the conductive layer, and performing a rapid thermal oxidation (RTO) anneal. The thin HTO film may be deposited before or after performing the RTO anneal. The sidewall oxide formation process may provide an improved memory cell as compared with known prior art techniques, e.g., in terms of endurance and data retention.

公开(公告)号：US20170170303A1

公开(公告)日：2017-06-15

申请号：US15375094

申请日：2016-12-11

Applicant: Microchip Technology Incorporated

Inventor： Jack Wong ,  Sajid Kabeer ,  Mel Hymas ,  Santosh Murali ,  Brad Kopp

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/788

CPC classification number: H01L29/66825 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02318 ,  H01L21/02323 ,  H01L21/02337 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/7881

Abstract: Methods of fabricating a memory cell of a semiconductor device, e.g., an EEPROM cell, having a sidewall oxide are disclosed. A memory cell structure may be formed including a floating gate and an ONO film over the conductive layer. A sidewall oxide may be formed on a side surface of the floating gate by a process including depositing a thin high temperature oxide (HTO) film on the side surface of the conductive layer, and performing a rapid thermal oxidation (RTO) anneal. The thin HTO film may be deposited before or after performing the RTO anneal. The sidewall oxide formation process may provide an improved memory cell as compared with known prior art techniques, e.g., in terms of endurance and data retention.