公开(公告)号：US09865814B2

公开(公告)日：2018-01-09

申请号：US15200322

申请日：2016-07-01

Applicant: Microchip Technology Incorporated

Inventor： Paul Fest ,  James Walls

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1273 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/085 ,  H01L45/122 ,  H01L45/1233 ,  H01L45/142 ,  H01L45/144 ,  H01L45/145 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1608 ,  H01L45/1675

Abstract: A method of forming a resistive memory cell, e.g., a CBRAM or ReRAM, may include forming a bottom electrode layer, forming an oxide region of an exposed area of the bottom electrode, removing a region of the bottom electrode layer proximate the oxide region to form a bottom electrode having a pointed tip or edge region, and forming first and second electrolyte regions and first and second top electrodes over the bottom electrode to define distinct first and second memory elements. The first memory element defines a first conductive filament/vacancy chain path from the first portion of the bottom electrode pointed tip region to the first top electrode via the first electrolyte region, and second memory element defines a second conductive filament/vacancy chain path from the second portion of the bottom electrode pointed tip region to the second top electrode via the second electrolyte region.

公开(公告)号：US20160315257A1

公开(公告)日：2016-10-27

申请号：US15200322

申请日：2016-07-01

Applicant: Microchip Technology Incorporated

Inventor： Paul Fest ,  James Walls

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1273 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/085 ,  H01L45/122 ,  H01L45/1233 ,  H01L45/142 ,  H01L45/144 ,  H01L45/145 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1608 ,  H01L45/1675

Abstract: A method of forming a resistive memory cell, e.g., a CBRAM or ReRAM, may include forming a bottom electrode layer, forming an oxide region of an exposed area of the bottom electrode, removing a region of the bottom electrode layer proximate the oxide region to form a bottom electrode having a pointed tip or edge region, and forming first and second electrolyte regions and first and second top electrodes over the bottom electrode to define distinct first and second memory elements. The first memory element defines a first conductive filament/vacancy chain path from the first portion of the bottom electrode pointed tip region to the first top electrode via the first electrolyte region, and second memory element defines a second conductive filament/vacancy chain path from the second portion of the bottom electrode pointed tip region to the second top electrode via the second electrolyte region.

Abstract translation: 形成电阻存储单元（例如CBRAM或ReRAM）的方法可以包括形成底部电极层，形成底部电极的暴露区域的氧化物区域，去除靠近氧化物区域的底部电极层的区域 形成具有尖端或边缘区域的底部电极，以及在底部电极上形成第一和第二电解质区域以及第一和第二顶部电极以限定不同的第一和第二存储元件。 第一存储元件限定了从底部电极尖端区域的第一部分经由第一电解质区域到第一顶部电极的第一导电细丝/空位链路径，并且第二存储元件限定了来自第一电解质区域的第二导电细丝/空位链路径 底部电极尖端区域的第二部分经由第二电解质区域延伸到第二顶部电极。

公开(公告)号：US09385313B2

公开(公告)日：2016-07-05

申请号：US14184331

申请日：2014-02-19

Applicant: Microchip Technology Incorporated

Inventor： Paul Fest ,  James Walls

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1273 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/085 ,  H01L45/122 ,  H01L45/1233 ,  H01L45/142 ,  H01L45/144 ,  H01L45/145 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1608 ,  H01L45/1675

Abstract: A method of forming a resistive memory cell, e.g., a CBRAM or ReRAM, may include forming a bottom electrode layer, forming an oxide region of an exposed area of the bottom electrode, removing a region of the bottom electrode layer proximate the oxide region to form a bottom electrode having a pointed tip or edge region, and forming first and second electrolyte regions and first and second top electrodes over the bottom electrode to define distinct first and second memory elements. The first memory element defines a first conductive filament/vacancy chain path from the first portion of the bottom electrode pointed tip region to the first top electrode via the first electrolyte region, and second memory element defines a second conductive filament/vacancy chain path from the second portion of the bottom electrode pointed tip region to the second top electrode via the second electrolyte region.

Abstract translation: 形成电阻存储单元（例如CBRAM或ReRAM）的方法可以包括形成底部电极层，形成底部电极的暴露区域的氧化物区域，去除靠近氧化物区域的底部电极层的区域 形成具有尖端或边缘区域的底部电极，以及在底部电极上形成第一和第二电解质区域以及第一和第二顶部电极以限定不同的第一和第二存储元件。 第一存储元件限定了从底部电极尖端区域的第一部分经由第一电解质区域到第一顶部电极的第一导电细丝/空位链路径，并且第二存储元件限定了来自第一电解质区域的第二导电细丝/空位链路径 底部电极尖端区域的第二部分经由第二电解质区域延伸到第二顶部电极。

公开(公告)号：US20160190442A1

公开(公告)日：2016-06-30

申请号：US15065354

申请日：2016-03-09

Applicant: Microchip Technology Incorporated

Inventor： Paul Fest ,  James Walls

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1273 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/085 ,  H01L45/122 ,  H01L45/1233 ,  H01L45/141 ,  H01L45/142 ,  H01L45/144 ,  H01L45/145 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1675

Abstract: A method of forming a resistive memory cell, e.g., a CBRAM or ReRAM, may include forming a bottom electrode layer, oxidizing an exposed region of the bottom electrode layer to form an oxide region, removing a region of the bottom electrode layer proximate the oxide region, thereby forming a bottom electrode having a pointed tip region adjacent the oxide region, and forming an electrolyte region and top electrode over at least a portion of the bottom electrode and oxide region, such that the electrolyte region is arranged between the pointed tip region of the bottom electrode and the top electrode, and provides a path for conductive filament or vacancy chain formation from the pointed tip region of the bottom electrode to the top electrode when a voltage bias is applied to the memory cell. A memory cell and memory cell array formed by such method are also disclosed.

Abstract translation: 形成电阻式存储单元（例如CBRAM或ReRAM）的方法可以包括形成底部电极层，氧化底部电极层的暴露区域以形成氧化物区域，去除接近氧化物的底部电极层的区域 从而形成具有与氧化物区域相邻的尖端区域的底部电极，并且在底部电极和氧化物区域的至少一部分上形成电解质区域和顶部电极，使得电解质区域配置在尖端区域 并且当将电压偏压施加到存储单元时，提供从底电极的尖尖区域到顶电极的导电细丝或空位链形成的路径。 还公开了通过这种方法形成的存储单元和存储单元阵列。

公开(公告)号：US09362496B2

公开(公告)日：2016-06-07

申请号：US14183738

申请日：2014-02-19

Applicant: Microchip Technology Incorporated

Inventor： James Walls ,  Paul Fest

IPC: H01L47/00 ,  H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1253 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/124 ,  H01L45/1246 ,  H01L45/1273 ,  H01L45/142 ,  H01L45/144 ,  H01L45/145 ,  H01L45/146 ,  H01L45/16

Abstract: A resistive memory cell, e.g., CBRAM or ReRAM cell, may include a top electrode an a trench-shaped bottom electrode structure defining a bottom electrode connection and a sidewall extending from a first sidewall region adjacent the bottom electrode connection to a tip region defining a tip surface facing generally away from the bottom electrode connection, and wherein the tip surface facing away from the bottom electrode connection has a tip thickness that is less than a thickness of the first sidewall region adjacent the bottom electrode connection. An electrolyte switching region is arranged between the top electrode and the bottom electrode sidewall tip region to provide a path for the formation of a conductive filament or vacancy chain from the bottom electrode sidewall tip surface of the top electrode, via the electrolyte switching region, when a voltage bias is applied to the resistive memory cell.

Abstract translation: 电阻式存储器单元（例如CBRAM或ReRAM单元）可以包括顶部电极，限定底部电极连接的沟槽状底部电极结构和从邻近底部电极连接的第一侧壁区域延伸到限定一个 尖端表面大致远离底部电极连接，并且其中背离底部电极连接的尖端表面的尖端厚度小于邻近底部电极连接的第一侧壁区域的厚度。 电解质开关区域布置在顶部电极和底部电极侧壁顶端区域之间，以提供用于通过电解质切换区域从顶部电极的底部电极侧壁顶端表面形成导电细丝或空位链的路径，当时 电压偏置被施加到电阻性存储单元。

公开(公告)号：US10700077B2

公开(公告)日：2020-06-30

申请号：US15921858

申请日：2018-03-15

Applicant: Microchip Technology Incorporated

Inventor： Mel Hymas ,  James Walls ,  Sonu Daryanani

IPC: H01L27/11517 ,  H01L27/105 ,  H01L21/28 ,  H01L29/788 ,  H01L29/423 ,  H01L29/66

Abstract: A memory cell, e.g., a flash memory cell, includes a substrate, a flat-topped floating gate formed over the substrate, and a flat-topped oxide region formed over the flat-topped floating gate. The flat-topped floating gate may have a sidewall with a generally concave shape that defines an acute angle at a top corner of the floating gate, which may improve a program or erase efficiency of the memory cell. The flat-topped floating gate and overlying oxide region may be formed with without a floating gate thermal oxidation that forms a conventional “football oxide.” A word line and a separate erase gate may be formed over the floating gate and oxide region. The erase gate may overlap the floating gate by a substantially greater distance than the word line overlaps the floating gate, which may allow the program and erase coupling to the floating gate to be optimized independently.

公开(公告)号：US20190207006A1

公开(公告)日：2019-07-04

申请号：US15922571

申请日：2018-03-15

Applicant: Microchip Technology Incorporated

Inventor： Mel Hymas ,  James Walls ,  Sonu Daryanani

IPC: H01L29/423 ,  H01L27/11521

CPC classification number: H01L29/42328 ,  G11C16/0408 ,  G11C16/08 ,  G11C16/14 ,  H01L27/11521 ,  H01L29/7841

Abstract: A memory cell, e.g., a flash memory cell, includes a substrate, a floating gate formed over the substrate, and a word line and an erase gate formed over the floating gate. The word line overlaps the floating gate by a first lateral overlap distance, and the erase gate overlaps the floating gate by a second lateral overlap distance that is substantially greater than the first lateral distance. This configuration allows the program and erase coupling to the floating gate to be optimized independently, e.g., to decrease or minimize the program current and/or increase or maximize the erase current for the cell.

公开(公告)号：US20160190441A1

公开(公告)日：2016-06-30

申请号：US15065193

申请日：2016-03-09

Applicant: Microchip Technology Incorporated

Inventor： James Walls ,  Paul Fest

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1273 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/142 ,  H01L45/144 ,  H01L45/145 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1608 ,  H01L45/1675 ,  H01L45/1691

Abstract: A method of forming a resistive memory cell, e.g., a CBRAM or ReRAM cell, may include: forming a plurality of bottom electrode connections, depositing a bottom electrode layer over the bottom electrode connections, performing a first etch to remove portions of the bottom electrode layer such that the remaining bottom electrode layer defines at least one sloped surface, forming an oxidation layer on each sloped surface of the remaining bottom electrode layer, performing a second etch on the remaining bottom electrode layer and oxidation layer on each sloped surface to define at least one upwardly-pointing bottom electrode region above each bottom electrode connection, each upwardly-pointing bottom electrode region defining a bottom electrode tip, and forming an electrolyte region and a top electrode over each bottom electrode tip such that the electrolyte region is arranged between the top electrode and the respective bottom electrode top.

Abstract translation: 形成电阻式存储单元（例如CBRAM或ReRAM单元）的方法可以包括：形成多个底部电极连接，在底部电极连接上沉积底部电极层，执行第一次蚀刻以去除底部电极的部分 层，使得剩余的底部电极层限定至少一个倾斜表面，在剩余底部电极层的每个倾斜表面上形成氧化层，对每个倾斜表面上的剩余底部电极层和氧化层进行第二次蚀刻，以在 在每个底部电极连接上方的至少一个向上指向的底部电极区域，每个向上指向的底部电极区域限定底部电极尖端，以及在每个底部电极尖端上形成电解质区域和顶部电极，使得电解质区域布置在 顶部电极和相应的底部电极顶部。

公开(公告)号：US20150236255A1

公开(公告)日：2015-08-20

申请号：US14184331

申请日：2014-02-19

Applicant: Microchip Technology Incorporated

Inventor： Paul Fest ,  James Walls

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1273 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/085 ,  H01L45/122 ,  H01L45/1233 ,  H01L45/142 ,  H01L45/144 ,  H01L45/145 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1608 ,  H01L45/1675

Abstract: A method of forming a resistive memory cell, e.g., a CBRAM or ReRAM, may include forming a bottom electrode layer, forming an oxide region of an exposed area of the bottom electrode, removing a region of the bottom electrode layer proximate the oxide region to form a bottom electrode having a pointed tip or edge region, and forming first and second electrolyte regions and first and second top electrodes over the bottom electrode to define distinct first and second memory elements. The first memory element defines a first conductive filament/vacancy chain path from the first portion of the bottom electrode pointed tip region to the first top electrode via the first electrolyte region, and second memory element defines a second conductive filament/vacancy chain path from the second portion of the bottom electrode pointed tip region to the second top electrode via the second electrolyte region.

Abstract translation: 形成电阻存储单元（例如CBRAM或ReRAM）的方法可以包括形成底部电极层，形成底部电极的暴露区域的氧化物区域，去除靠近氧化物区域的底部电极层的区域 形成具有尖端或边缘区域的底部电极，以及在底部电极上形成第一和第二电解质区域以及第一和第二顶部电极以限定不同的第一和第二存储元件。 第一存储元件限定了从底部电极尖端区域的第一部分经由第一电解质区域到第一顶部电极的第一导电细丝/空位链路径，并且第二存储元件限定了来自第一电解质区域的第二导电细丝/空位链路径 底部电极尖端区域的第二部分经由第二电解质区域延伸到第二顶部电极。

公开(公告)号：US20140264246A1

公开(公告)日：2014-09-18

申请号：US14183738

申请日：2014-02-19

Applicant: MICROCHIP TECHNOLOGY INCORPORATED

Inventor： James Walls ,  Paul Fest

IPC: H01L45/00

CPC classification number: H01L45/1253 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/124 ,  H01L45/1246 ,  H01L45/1273 ,  H01L45/142 ,  H01L45/144 ,  H01L45/145 ,  H01L45/146 ,  H01L45/16

Abstract: A resistive memory cell, e.g., CBRAM or ReRAM cell, may include a top electrode an a trench-shaped bottom electrode structure defining a bottom electrode connection and a sidewall extending from a first sidewall region adjacent the bottom electrode connection to a tip region defining a tip surface facing generally away from the bottom electrode connection, and wherein the tip surface facing away from the bottom electrode connection has a tip thickness that is less than a thickness of the first sidewall region adjacent the bottom electrode connection. An electrolyte switching region is arranged between the top electrode and the bottom electrode sidewall tip region to provide a path for the formation of a conductive filament or vacancy chain from the bottom electrode sidewall tip surface of the top electrode, via the electrolyte switching region, when a voltage bias is applied to the resistive memory cell.

Abstract translation: 电阻式存储器单元（例如CBRAM或ReRAM单元）可以包括顶部电极，限定底部电极连接的沟槽状底部电极结构和从邻近底部电极连接的第一侧壁区域延伸到限定一个 尖端表面大致远离底部电极连接，并且其中背离底部电极连接的尖端表面的尖端厚度小于邻近底部电极连接的第一侧壁区域的厚度。 电解质开关区域布置在顶部电极和底部电极侧壁顶端区域之间，以便通过电解质切换区域从顶部电极的底部电极侧壁顶端表面提供用于形成导电细丝或空位链的路径，当时 电压偏置被施加到电阻性存储单元。