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公开(公告)号：US20160190441A1
公开(公告)日：2016-06-30
申请号：US15065193
申请日：2016-03-09
Applicant: Microchip Technology Incorporated
Inventor： James Walls , Paul Fest
CPC classification number: H01L45/1273 , H01L27/2463 , H01L45/08 , H01L45/085 , H01L45/1233 , H01L45/142 , H01L45/144 , H01L45/145 , H01L45/146 , H01L45/16 , H01L45/1608 , H01L45/1675 , H01L45/1691
Abstract: A method of forming a resistive memory cell, e.g., a CBRAM or ReRAM cell, may include: forming a plurality of bottom electrode connections, depositing a bottom electrode layer over the bottom electrode connections, performing a first etch to remove portions of the bottom electrode layer such that the remaining bottom electrode layer defines at least one sloped surface, forming an oxidation layer on each sloped surface of the remaining bottom electrode layer, performing a second etch on the remaining bottom electrode layer and oxidation layer on each sloped surface to define at least one upwardly-pointing bottom electrode region above each bottom electrode connection, each upwardly-pointing bottom electrode region defining a bottom electrode tip, and forming an electrolyte region and a top electrode over each bottom electrode tip such that the electrolyte region is arranged between the top electrode and the respective bottom electrode top.
Abstract translation: 形成电阻式存储单元（例如CBRAM或ReRAM单元）的方法可以包括：形成多个底部电极连接，在底部电极连接上沉积底部电极层，执行第一次蚀刻以去除底部电极的部分 层，使得剩余的底部电极层限定至少一个倾斜表面，在剩余底部电极层的每个倾斜表面上形成氧化层，对每个倾斜表面上的剩余底部电极层和氧化层进行第二次蚀刻，以在 在每个底部电极连接上方的至少一个向上指向的底部电极区域，每个向上指向的底部电极区域限定底部电极尖端，以及在每个底部电极尖端上形成电解质区域和顶部电极，使得电解质区域布置在 顶部电极和相应的底部电极顶部。
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公开(公告)号：US20150236255A1
公开(公告)日：2015-08-20
申请号：US14184331
申请日：2014-02-19
Applicant: Microchip Technology Incorporated
Inventor： Paul Fest , James Walls
CPC classification number: H01L45/1273 , H01L27/2463 , H01L45/08 , H01L45/085 , H01L45/122 , H01L45/1233 , H01L45/142 , H01L45/144 , H01L45/145 , H01L45/146 , H01L45/16 , H01L45/1608 , H01L45/1675
Abstract: A method of forming a resistive memory cell, e.g., a CBRAM or ReRAM, may include forming a bottom electrode layer, forming an oxide region of an exposed area of the bottom electrode, removing a region of the bottom electrode layer proximate the oxide region to form a bottom electrode having a pointed tip or edge region, and forming first and second electrolyte regions and first and second top electrodes over the bottom electrode to define distinct first and second memory elements. The first memory element defines a first conductive filament/vacancy chain path from the first portion of the bottom electrode pointed tip region to the first top electrode via the first electrolyte region, and second memory element defines a second conductive filament/vacancy chain path from the second portion of the bottom electrode pointed tip region to the second top electrode via the second electrolyte region.
Abstract translation: 形成电阻存储单元（例如CBRAM或ReRAM）的方法可以包括形成底部电极层，形成底部电极的暴露区域的氧化物区域，去除靠近氧化物区域的底部电极层的区域 形成具有尖端或边缘区域的底部电极，以及在底部电极上形成第一和第二电解质区域以及第一和第二顶部电极以限定不同的第一和第二存储元件。 第一存储元件限定了从底部电极尖端区域的第一部分经由第一电解质区域到第一顶部电极的第一导电细丝/空位链路径，并且第二存储元件限定了来自第一电解质区域的第二导电细丝/空位链路径 底部电极尖端区域的第二部分经由第二电解质区域延伸到第二顶部电极。
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公开(公告)号：US20140264891A1
公开(公告)日：2014-09-18
申请号：US13838784
申请日：2013-03-15
Applicant: MICROCHIP TECHNOLOGY INCORPORATED
Inventor： Paul Fest
IPC: H01L21/768
CPC classification number: H01L21/76814 , H01L21/76838 , H01L21/76877
Abstract: A spacer etching process produces ultra-narrow conductive lines in a plurality of semiconductor dice. Sub-lithographic patterning of the conductive lines are compatible with existing aluminum and copper backend processing. A first dielectric is deposited onto the semiconductor dice and trenches are formed therein. A conductive film is deposited onto the first dielectric and the trench surfaces. All planar conductive film is removed from the faces of the semiconductor dice and bottoms of the trenches, leaving only conductive films on the trench walls, whereby “fence conductors” are created therefrom. Thereafter the gap between the conductive films on the trench walls are filled in with insulating material. A top portion of the insulated gap fill is thereafter removed to expose the tops of the fence conductors. Portions of the fence conductors and surrounding insulating materials are removed at appropriate locations to produce desired conductor patterns comprising isolated fence conductors.
Abstract translation: 间隔蚀刻工艺在多个半导体管芯中产生超窄导电线。 导电线的次平版印刷图案与现有的铝和铜后端处理兼容。 第一电介质沉积在半导体晶片上，并在其中形成沟槽。 导电膜沉积在第一电介质和沟槽表面上。 从沟槽的半导体晶片和底部的表面去除所有的平面导电膜，仅在沟槽壁上留下导电膜，从而由此形成“栅栏导体”。 此后，沟槽壁上的导电膜之间的间隙用绝缘材料填充。 此后，绝缘间隙填充的顶部被去除以露出栅栏导体的顶部。 栅栏导体和围绕的绝缘材料的部分在合适的位置被去除以产生包括隔离栅栏导体的期望的导体图案。
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公开(公告)号：US20140264246A1
公开(公告)日：2014-09-18
申请号：US14183738
申请日：2014-02-19
Applicant: MICROCHIP TECHNOLOGY INCORPORATED
Inventor： James Walls , Paul Fest
IPC: H01L45/00
CPC classification number: H01L45/1253 , H01L27/2463 , H01L45/08 , H01L45/085 , H01L45/1233 , H01L45/124 , H01L45/1246 , H01L45/1273 , H01L45/142 , H01L45/144 , H01L45/145 , H01L45/146 , H01L45/16
Abstract: A resistive memory cell, e.g., CBRAM or ReRAM cell, may include a top electrode an a trench-shaped bottom electrode structure defining a bottom electrode connection and a sidewall extending from a first sidewall region adjacent the bottom electrode connection to a tip region defining a tip surface facing generally away from the bottom electrode connection, and wherein the tip surface facing away from the bottom electrode connection has a tip thickness that is less than a thickness of the first sidewall region adjacent the bottom electrode connection. An electrolyte switching region is arranged between the top electrode and the bottom electrode sidewall tip region to provide a path for the formation of a conductive filament or vacancy chain from the bottom electrode sidewall tip surface of the top electrode, via the electrolyte switching region, when a voltage bias is applied to the resistive memory cell.
Abstract translation: 电阻式存储器单元（例如CBRAM或ReRAM单元）可以包括顶部电极，限定底部电极连接的沟槽状底部电极结构和从邻近底部电极连接的第一侧壁区域延伸到限定一个 尖端表面大致远离底部电极连接，并且其中背离底部电极连接的尖端表面的尖端厚度小于邻近底部电极连接的第一侧壁区域的厚度。 电解质开关区域布置在顶部电极和底部电极侧壁顶端区域之间，以便通过电解质切换区域从顶部电极的底部电极侧壁顶端表面提供用于形成导电细丝或空位链的路径，当时 电压偏置被施加到电阻性存储单元。
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公开(公告)号：US11508500B2
公开(公告)日：2022-11-22
申请号：US17071442
申请日：2020-10-15
Applicant: Microchip Technology Incorporated
Inventor： Paul Fest , Jacob Williams , Josh Kaufman
Abstract: A method is provided for forming a thin film resistor (TFR) in an integrated circuit (IC) device. A TFR film is formed and annealed over an IC structure including IC elements and IC element contacts. At least one TFR cap layer is formed, and a TFR etch defines a TFR element from the TFR film. A TFR contact etch forms TFR contact openings over the TFR element, and a metal layer is formed over the IC structure and extending into the TFR contact openings to form metal contacts to the IC element contacts and the TFR element. The TFR cap layer(s), e.g., SiN cap and/or oxide cap formed over the TFR film, may (a) provide an etch stop during the TFR contact etch and/or (b) provide a hardmask during the TFR etch, which may eliminate the use of a photomask and thereby eliminate post-etch removal of photomask polymer.
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Patent Agency Ranking
公开(公告)号：US20210272725A1
公开(公告)日：2021-09-02
申请号：US17071442
申请日：2020-10-15
Applicant: Microchip Technology Incorporated
Inventor： Paul Fest , Jacob Williams , Josh Kaufman
Abstract: A method is provided for forming a thin film resistor (TFR) in an integrated circuit (IC) device. A TFR film is formed and annealed over an IC structure including IC elements and IC element contacts. At least one TFR cap layer is formed, and a TFR etch defines a TFR element from the TFR film. A TFR contact etch forms TFR contact openings over the TFR element, and a metal layer is formed over the IC structure and extending into the TFR contact openings to form metal contacts to the IC element contacts and the TFR element. The TFR cap layer(s), e.g., SiN cap and/or oxide cap formed over the TFR film, may (a) provide an etch stop during the TFR contact etch and/or (b) provide a hardmask during the TFR etch, which may eliminate the use of a photomask and thereby eliminate post-etch removal of photomask polymer.
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公开(公告)号：US11088024B2
公开(公告)日：2021-08-10
申请号：US16450391
申请日：2019-06-24
Applicant: Microchip Technology Incorporated
Inventor： Paul Fest
IPC: H01L21/768 , H01L21/311 , H01L49/02
Abstract: A method is provided for forming a thin film resistor (TFR) in an integrated circuit (IC) including IC elements, e.g., memory components. A first contact etch stop layer is formed over the IC elements. A TFR layer stack including a TFR etch stop layer, a TFR film layer, and a second contact etch stop layer is formed over the first contact etch stop layer, and in some cases over one or more pre-metal dielectric layers. A patterned mask is formed over the IC stack, and the stack is etched, through both the first and second contact etch stop layers, to simultaneously form (a) first contact openings exposing contact regions of the IC elements and (b) second contact opening(s) exposing the TFR film layer. The first and second contact openings are filled with conductive material to form conductive contacts to the IC elements and the TFR film layer.
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公开(公告)号：US20200328115A1
公开(公告)日：2020-10-15
申请号：US16450391
申请日：2019-06-24
Applicant: Microchip Technology Incorporated
Inventor： Paul Fest
IPC: H01L21/768 , H01L49/02 , H01L21/311
Abstract: A method is provided for forming a thin film resistor (TFR) in an integrated circuit (IC) including IC elements, e.g., memory components. A first contact etch stop layer is formed over the IC elements. A TFR layer stack including a TFR etch stop layer, a TFR film layer, and a second contact etch stop layer is formed over the first contact etch stop layer, and in some cases over one or more pre-metal dielectric layers. A patterned mask is formed over the IC stack, and the stack is etched, through both the first and second contact etch stop layers, to simultaneously form (a) first contact openings exposing contact regions of the IC elements and (b) second contact opening(s) exposing the TFR film layer. The first and second contact openings are filled with conductive material to form conductive contacts to the IC elements and the TFR film layer.
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公开(公告)号：US20180287057A1
公开(公告)日：2018-10-04
申请号：US16001332
申请日：2018-06-06
Applicant: Microchip Technology Incorporated
Inventor： James Walls , Paul Fest
IPC: H01L45/00
Abstract: A method of forming a resistive memory cell, e.g., a CBRAM or ReRAM cell, may include forming a plurality of bottom electrode connections, depositing a bottom electrode layer over the bottom electrode connections, performing an etch to remove portions of the bottom electrode layer to form at least one upwardly-pointing bottom electrode region above the bottom electrode connections, each upwardly-pointing bottom electrode region defining a bottom electrode tip, and forming an electrolyte region and a top electrode over each bottom electrode tip such that the electrolyte region is arranged between the top electrode and the respective bottom electrode top.
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公开(公告)号：US09917251B2
公开(公告)日：2018-03-13
申请号：US15065354
申请日：2016-03-09
Applicant: Microchip Technology Incorporated
Inventor： Paul Fest , James Walls
CPC classification number: H01L45/1273 , H01L27/2463 , H01L45/08 , H01L45/085 , H01L45/122 , H01L45/1233 , H01L45/141 , H01L45/142 , H01L45/144 , H01L45/145 , H01L45/146 , H01L45/16 , H01L45/1675
Abstract: A method of forming a resistive memory cell, e.g., a CBRAM or ReRAM, may include forming a bottom electrode layer, oxidizing an exposed region of the bottom electrode layer to form an oxide region, removing a region of the bottom electrode layer proximate the oxide region, thereby forming a bottom electrode having a pointed tip region adjacent the oxide region, and forming an electrolyte region and top electrode over at least a portion of the bottom electrode and oxide region, such that the electrolyte region is arranged between the pointed tip region of the bottom electrode and the top electrode, and provides a path for conductive filament or vacancy chain formation from the pointed tip region of the bottom electrode to the top electrode when a voltage bias is applied to the memory cell. A memory cell and memory cell array formed by such method are also disclosed.
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