Invention Grant
- Patent Title: Resistive memory cell having a reduced conductive path area
- Patent Title (中): 具有减小的导电路径面积的电阻式存储单元
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Application No.: US14184331Application Date: 2014-02-19
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Publication No.: US09385313B2Publication Date: 2016-07-05
- Inventor: Paul Fest , James Walls
- Applicant: Microchip Technology Incorporated
- Applicant Address: US AZ Chandler
- Assignee: MICROCHIP TECHNOLOGY INCORPORATED
- Current Assignee: MICROCHIP TECHNOLOGY INCORPORATED
- Current Assignee Address: US AZ Chandler
- Agency: Slayden Grubert Beard PLLC
- Main IPC: H01L45/00
- IPC: H01L45/00 ; H01L27/24

Abstract:
A method of forming a resistive memory cell, e.g., a CBRAM or ReRAM, may include forming a bottom electrode layer, forming an oxide region of an exposed area of the bottom electrode, removing a region of the bottom electrode layer proximate the oxide region to form a bottom electrode having a pointed tip or edge region, and forming first and second electrolyte regions and first and second top electrodes over the bottom electrode to define distinct first and second memory elements. The first memory element defines a first conductive filament/vacancy chain path from the first portion of the bottom electrode pointed tip region to the first top electrode via the first electrolyte region, and second memory element defines a second conductive filament/vacancy chain path from the second portion of the bottom electrode pointed tip region to the second top electrode via the second electrolyte region.
Public/Granted literature
- US20150236255A1 Resistive Memory Cell having a Reduced Conductive Path Area Public/Granted day:2015-08-20
Information query
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