公开(公告)号：US20250165816A1

公开(公告)日：2025-05-22

申请号：US18747429

申请日：2024-06-18

Applicant: Microchip Technology Incorporated

Inventor： Chris NORRIE ,  Igor ZIPER ,  Pitamber SHUKLA

IPC: G06N5/04

Abstract: In some implementations, a controller may receive a request for an inference. The controller may determine, based on the received request for the inference, a first inference model of a plurality of inference models, to generate the inference. The controller may obtain, from a memory associated with an inference cache, first attribute data regarding first attributes of the first inference model. A location of the first attribute data, in the memory, may be determined using the inference cache. The attributes may include weights associated with the first inference model, biases associated with the first inference model, and a structure of the first inference model. The controller may utilize the first attribute data to generate the inference based on the request.

公开(公告)号：US20250165397A1

公开(公告)日：2025-05-22

申请号：US18731232

申请日：2024-05-31

Applicant: Microchip Technology Incorporated

Inventor： Pitamber SHUKLA ,  Chris NORRIE ,  Igor ZIPER ,  Srinivas YELISETTI

IPC: G06F12/06

Abstract: A controller may determine, using a machine learning model, reliability characteristic data associated with memory cells of a non-volatile memory device. The machine learning model may be trained using characterization data that identifies different reliability characteristic of one or more non-volatile memory devices. The controller may group, based on the reliability characteristic data, a first portion of the memory cells of the non-volatile memory device in a first management group, and a second portion of the memory cells of the non-volatile memory device in a second management group. The controller may manage, based on the reliability characteristic data, background scanning and logical to physical mapping of the first management group of memory cells, and the second management group of memory cells.

公开(公告)号：US20250165148A1

公开(公告)日：2025-05-22

申请号：US18622866

申请日：2024-03-29

Applicant: Microchip Technology Incorporated

Inventor： Pitamber SHUKLA ,  Chris NORRIE ,  Igor ZIPER

IPC: G06F3/06

Abstract: A controller, of a solid state drive (SSD), may perform, on one or more blocks of a non-volatile memory device of the SSD, read operations using pre-determined threshold voltages associated with two overlapped charge states. The read operations may be performed after a power-on condition following a power-off condition on the non-volatile memory device. The controller may determine, using a machine learning model, a change in threshold voltages associated with the two overlapped charge states, after the power-off condition. The machine learning model may determine the change in threshold voltages using bit error rates associated with the read operations. The machine learning model may be trained to determine changes in threshold voltages for the two overlapped charge states, after power-off conditions. The controller may determine adjusted threshold voltages associated with the two overlapped charge states based on the change in threshold voltages.

公开(公告)号：US20250159548A1

公开(公告)日：2025-05-15

申请号：US18943597

申请日：2024-11-11

Applicant: Microchip Technology Incorporated

Inventor： Battu Prakash Reddy ,  Varaprasad Palivela ,  Kranthi Kumar Ghanapuram ,  Naga Srujit Adimulam ,  Sunny Bazawada

IPC: H04W28/04

Abstract: A method may include obtaining samples associated with one or more symbols of a packet; determining at least one down-sampling point in a sequence of samples associated with a header portion of the packet; and utilizing samples associated with the determined down-sampling point to recover the one or more symbol and subsequent symbols.

公开(公告)号：US20250157714A1

公开(公告)日：2025-05-15

申请号：US18947733

申请日：2024-11-14

Applicant: Microchip Technology Incorporated

Inventor： Ganesh Shaga ,  Surendra Akkina ,  Sudheer Puttapudi

IPC: H01F27/00 ,  G01B7/30 ,  H01F5/04 ,  H01F17/02

Abstract: An apparatus includes a support structure and a sense coil comprising conductive traces on, or in, multiple layers of the support structure. The sense coil includes a first coil portion, a second coil portion, and first and second crossover connections. The first coil portion has M turns defining one or more in-phase lobes and the second coil portion has N turns defining one or more out-of-phase lobes. The first crossover connection connects an ending portion of an Mth turn of the first coil portion of an in-phase lobe to a starting portion of a first turn of the second coil portion of an out-of-phase lobe. The second crossover connection connects an ending portion of an Nth turn of the second coil portion of the out-of-phase lobe to a starting portion of a first turn of the first coil portion of the in-phase lobe.

公开(公告)号：US12301389B2

公开(公告)日：2025-05-13

申请号：US18417706

申请日：2024-01-19

Applicant: Microchip Technology Incorporated

Inventor： Ravish Soni

IPC: H04L25/03 ,  H03K5/133 ,  H03K17/687

Abstract: Decision feedback equalization (DFE) taps and related apparatuses and methods are disclosed. An apparatus includes a first electrically controllable switch, a second electrically controllable switch, and one or more delay elements. The first electrically controllable switch receives a history bit and selectively provides the history bit to gate terminals of first transistors of a DFE tap circuitry. The second electrically controllable switch receives a complementary history bit and selectively provides the complementary history bit to second gate terminals of second transistors of the DFE tap circuitry. The one or more delay elements provide one or more delayed data integration clock signals responsive to one or more data integration clock signals. A complementary delayed data integration clock signal controls switching of the first electrically controllable switch and the second electrically controllable switch.

公开(公告)号：US12298918B2

公开(公告)日：2025-05-13

申请号：US18065372

申请日：2022-12-13

Applicant: Microchip Technology Incorporated

Inventor： Brian Oostenbrink ,  Ariel Deneb Edward Sibley ,  Darshana Patel

IPC: G06F12/14 ,  G06F12/0831

Abstract: An apparatus may comprise an off-chip data storage device and a semiconductor device package including processing circuitry and an on-chip memory device, the off-chip data storage device including master data and portions of the computer-readable instructions. The processing circuitry may retrieve a master data that includes a digital signature that may be used to verify the master data and a hash table that may include hash information for others of the portions. The processing circuitry may also verify the master instructions responsive to the digital signature, retrieve a portion, calculate a hash value of the retrieved portion, and determine whether the calculated hash value correlates to hash information of the hash table.

公开(公告)号：US20250125779A1

公开(公告)日：2025-04-17

申请号：US18631132

申请日：2024-04-10

Applicant: Microchip Technology Incorporated

Inventor： Razvan Costache

IPC: H03F3/217 ,  H10N30/20

Abstract: An input signal may be converted into a first PWM signal and a second PWM signal at a PWM controller circuit. The first PWM signal and second signal output may drive a driver circuit. The driver circuit may receive a high-voltage supply from a boost converter or other power circuit. The driver circuit may include a high-side device and a low-side device. The output of the driver circuit may drive a filter circuit, the filter circuit comprising a filter capacitor, an inductor and a haptic actuator. The haptic actuator may produce a desired haptic response at the haptic actuator.

公开(公告)号：US20250124978A1

公开(公告)日：2025-04-17

申请号：US18914119

申请日：2024-10-12

Applicant: Microchip Technology Incorporated

Inventor： James Kim

IPC: G11C11/419 ,  G11C11/412

Abstract: An apparatus for dual edge memory write operation is provided. The apparatus may include a write enable circuit to receive a write enable signal for writing data to a memory cell, and a write driver circuit to receive a data signal and a complementary data signal, and output a bus signal and a complementary bus signal to the memory cell. The write driver circuit may be coupled to the write enable circuit. The write enable circuit may initiate a write operation to write data to the memory cell based on a falling edge of the write enable signal.

公开(公告)号：US12272639B2

公开(公告)日：2025-04-08

申请号：US17719548

申请日：2022-04-13

Applicant: Microchip Technology Incorporated

Inventor： Yaojian Leng

IPC: H01L23/52 ,  H01F17/00 ,  H01F27/28 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H10D1/20

Abstract: A device includes (a) an integrated inductor having an inductor wire and (b) a metal interconnect arrangement, both formed in an integrated circuit layer stack of alternating metal layers and via layers. At least a portion of the inductor wire is defined by an inductor element stack including multiple metal layer inductor elements formed in multiple respective metal layers, and multiple via layer inductor elements formed in multiple respective via layers and conductively connected to the metal layer inductor elements. Each via layer inductor element has a length of at least 1 μm in each of two lateral directions orthogonal to each other and perpendicular to the vertical direction. The metal interconnect arrangement includes metal layer interconnect elements formed in the respective metal layers, and interconnect vias formed in the respective via layers.