公开(公告)号：US20120074368A1

公开(公告)日：2012-03-29

申请号：US13181663

申请日：2011-07-13

申请人： Yoshitaka SASAGO ,  Masaharu KINOSHITA ,  Mitsuharu TAI ,  Akio SHIMA ,  Takashi KOBAYASHI

发明人： Yoshitaka SASAGO ,  Masaharu KINOSHITA ,  Mitsuharu TAI ,  Akio SHIMA ,  Takashi KOBAYASHI

IPC分类号： H01L47/00 ,  H01L21/3205

CPC分类号： H01L27/2445 ,  H01L27/0688 ,  H01L27/1021 ,  H01L45/1226 ,  H01L45/144

摘要： A semiconductor memory device having a diode and a transistor connected in series, which prevents carriers from going from the diode into the transistor, thereby reducing the possibility of transistor deterioration. A structure to annihilate carriers from the diode is provided between a channel layer of the transistor and a diode semiconductor layer of the diode where the carriers are generated.

摘要翻译： 具有串联连接的二极管和晶体管的半导体存储器件，其防止载流子从二极管进入晶体管，从而降低晶体管劣化的可能性。 在晶体管的沟道层和二极管的二极管半导体层之间提供从二极管湮灭载流子的结构，其中产生载流子。

公开(公告)号：US20120211717A1

公开(公告)日：2012-08-23

申请号：US13349653

申请日：2012-01-13

申请人： Masaharu KINOSHITA ,  Yoshitaka SASAGO ,  Takashi KOBAYASHI

发明人： Masaharu KINOSHITA ,  Yoshitaka SASAGO ,  Takashi KOBAYASHI

IPC分类号： H01L45/00 ,  H01L21/8239

CPC分类号： H01L45/06 ,  H01L27/2454 ,  H01L27/2472 ,  H01L45/144 ,  H01L45/1675

摘要： A semiconductor memory device in which the cell area can be decreased and the minimum feature size is not restricted by the thickness of the material forming the memory cell. In a semiconductor memory device, a gate insulating film, a channel extending in a direction X, and a resistance change element extending in the direction X are formed successively above multiple word lines extending in a direction Y, and a portion of the channel and a portion of the resistance change element are disposed above each of the plurality of the word lines. Such configuration can decrease the cell area and ensure the degree of design freedom.

摘要翻译： 可以减小单元面积并且最小特征尺寸不受形成存储单元的材料的厚度的半导体存储器件。 在半导体存储器件中，连续地沿着Y方向延伸的多个字线形成栅极绝缘膜，沿X方向延伸的沟道和沿X方向延伸的电阻变化元件，并且沟道的一部分和 电阻变化元件的一部分设置在多条字线的上方。 这样的配置可以减小单元面积并确保设计自由度。

公开(公告)号：US20110284817A1

公开(公告)日：2011-11-24

申请号：US13109985

申请日：2011-05-17

申请人： Yoshitaka SASAGO ,  Masaharu Kinoshita ,  Mitsuharu Tai ,  Takashi Kobayashi

发明人： Yoshitaka SASAGO ,  Masaharu Kinoshita ,  Mitsuharu Tai ,  Takashi Kobayashi

IPC分类号： H01L45/00 ,  H01L21/02

CPC分类号： H01L27/2481 ,  H01L27/1021 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2472

摘要： In a nonvolatile semiconductor memory device, there is provided a technique which promotes microfabrication by reducing a thickness of the device as suppressing an OFF current of a polysilicon diode which is a selective element. A polysilicon layer to which an impurity is doped at low concentration and which becomes an electric-field relaxation layer of the polysilicon diode which is a selective element of a resistance variable memory is formed so as to be divided into two or more layers such as polysilicon layers. In this manner, it is suppressed to form the crystal grain boundaries thoroughly penetrating between an n-type polysilicon layer and a p-type polysilicon layer in the electric-field relaxation layer, and therefore, it is prevented to generate a leakage current flowing through the crystal grain boundaries in application of a reverse-bias voltage without increasing a height of the polysilicon diode.

摘要翻译： 在非易失性半导体存储器件中，提供了一种通过减小作为选择元件的多晶硅二极管的截止电流来减小器件厚度来促进微细加工的技术。 形成以低浓度掺杂有杂质并作为电阻可变存储器的选择元件的多晶硅二极管的电场弛豫层的多晶硅层，以被分成两层或多层，例如多晶硅 层。 以这种方式抑制电场弛豫层中的n型多晶硅层和p型多晶硅层之间的晶粒边界完全透过，从而防止产生流过的漏电流 在不增加多晶硅二极管的高度的情况下施加反偏压的晶粒边界。

公开(公告)号：US20100058127A1

公开(公告)日：2010-03-04

申请号：US12469778

申请日：2009-05-21

申请人： Motoyasu TERAO ,  Satoru HANZAWA ,  Hitoshi KUME ,  Minoru OGUSHI ,  Yoshitaka SASAGO ,  Masaharu KINOSHITA ,  Norikatsu TAKAURA

发明人： Motoyasu TERAO ,  Satoru HANZAWA ,  Hitoshi KUME ,  Minoru OGUSHI ,  Yoshitaka SASAGO ,  Masaharu KINOSHITA ,  Norikatsu TAKAURA

IPC分类号： G06F11/26

CPC分类号： G11C13/0064 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0069 ,  G11C29/028 ,  G11C29/50 ,  G11C29/50008 ,  G11C2013/0054 ,  G11C2213/72

摘要： To realize a fast and highly reliable phase-change memory system of low power consumption, a semiconductor device includes: a memory device which includes a first memory array having a first area including a plurality of first memory cells and a second area including a plurality of second memory cells; a controller coupled to the memory device to issue a command to the memory device; and a condition table for storing a plurality of trial writing conditions. The controller performs trial writing in the plurality of second memory cells a plurality of times based on the plurality of trial writing conditions stored in the condition table, and determines writing conditions in the plurality of first memory cells based on a result of the trial writing. The memory device performs writing in the plurality of first memory cells based on the writing conditions instructed from the controller.

摘要翻译： 为了实现低功耗的快速且高度可靠的相变存储器系统，半导体器件包括：存储器件，其包括具有包括多个第一存储器单元的第一区域的第一存储器阵列和包括多个第一存储器单元的第二区域 第二存储单元; 控制器，其耦合到所述存储器设备以向所述存储器设备发出命令; 以及用于存储多个试写条件的条件表。 控制器基于存储在条件表中的多个试写条件，在多个第二存储单元中执行多次尝试写入，并且基于试写的结果来确定多个第一存储单元中的写入条件。 存储器件基于从控制器指示的写入条件在多个第一存储器单元中执行写入。

公开(公告)号：US20090267047A1

公开(公告)日：2009-10-29

申请号：US12430539

申请日：2009-04-27

申请人： Yoshitaka SASAGO ,  Riichiro TAKEMURA ,  Masaharu KINOSHITA ,  Toshiyuki MINE ,  Akio SHIMA ,  Hideyuki MATSUOKA ,  Mutsuko HATANO ,  Norikatsu TAKAURA

发明人： Yoshitaka SASAGO ,  Riichiro TAKEMURA ,  Masaharu KINOSHITA ,  Toshiyuki MINE ,  Akio SHIMA ,  Hideyuki MATSUOKA ,  Mutsuko HATANO ,  Norikatsu TAKAURA

IPC分类号： H01L47/00

CPC分类号： H01L27/2481 ,  H01L21/02532 ,  H01L21/02675 ,  H01L27/2409 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/146

摘要： The present invention can promote the large capacity, high performance and high reliability of a semiconductor memory device by realizing high-performance of both the semiconductor device and a memory device when the semiconductor memory device is manufactured by stacking a memory device such as ReRAM or the phase change memory and the semiconductor device. After a polysilicon forming a selection device is deposited in an amorphous state at a low temperature, the crystallization of the polysilicon and the activation of impurities are briefly performed with heat treatment by laser annealing. When laser annealing is performed, the recording material located below the silicon subjected to the crystallization is completely covered with a metal film or with the metal film and an insulating film, thereby making it possible to suppress a temperature increase at the time of performing the annealing and to reduce the thermal load of the recording material.

摘要翻译： 本发明可以通过实现半导体器件和存储器件的高性能来促进半导体存储器件的大容量，高性能和高可靠性，当半导体存储器件通过堆叠诸如ReRAM的存储器件或 相变存储器和半导体器件。 在低温下以非晶态沉积形成选择器件的多晶硅后，通过激光退火的热处理来简单地进行多晶硅的结晶化和杂质的活化。 当进行激光退火时，位于被结晶的硅下方的记录材料完全被金属膜或金属膜和绝缘膜覆盖，从而可以抑制进行退火时的温度升高 并降低记录材料的热负荷。

公开(公告)号：US20080261365A1

公开(公告)日：2008-10-23

申请号：US11865657

申请日：2007-10-01

申请人： Yoshitaka SASAGO ,  Takashi Kobayashi

发明人： Yoshitaka SASAGO ,  Takashi Kobayashi

IPC分类号： H01L21/8247

CPC分类号： H01L29/7881 ,  G11C16/0483 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/40114 ,  H01L29/42328

摘要： A technology realizing decreases of capacitance between the adjoining floating gates and of the threshold voltage shift caused by interference between the adjoining memory cells in a nonvolatile semiconductor memory device with the advances of miniaturization in the period following the 90 nm generation. By having the floating gate 3 of a memory cell with an inverse T-shape and the dimension of a part of the floating gate through the control gate 4 and the second insulator film 8 being smaller than the bottom part of the floating gate, the effects of a threshold voltage shift is reduced maintaining the adequate area of the gap between the floating gate 3 and the control gate 4, decreasing the opposing area of the gap of the floating gates 3 underneath the adjoining word lines WL, maintaining the capacity coupling ratio between the floating gate 3 and the control gate, and reducing the opposing area of the gap of the adjoining floating gates 3.

摘要翻译： 一种实现相邻浮栅之间的电容减小的技术和由非易失性半导体存储器件中相邻的存储单元之间的干扰引起的阈值电压偏移与90nm代之后的周期内的小型化的进步。 通过使具有逆T形的存储单元的浮置栅极3和通过控制栅极4和第二绝缘膜8的一部分浮动栅极的尺寸小于浮动栅极的底部的尺寸， 维持阈值电压偏移的维持维持浮动栅极3和控制栅极4之间的间隙的适当面积，减小相邻字线WL下面的浮动栅极3的间隙的相对面积，从而保持 浮动栅极3和控制栅极，并且减小邻接的浮动栅极3的间隙的相对面积。

公开(公告)号：US20090242868A1

公开(公告)日：2009-10-01

申请号：US12370417

申请日：2009-02-12

申请人： Kenzo KUROTSUCHI ,  Motoyasu TERAO ,  Norikatsu TAKAURA ,  Yoshihisa FUJISAKI ,  Kazuo ONO ,  Yoshitaka SASAGO

发明人： Kenzo KUROTSUCHI ,  Motoyasu TERAO ,  Norikatsu TAKAURA ,  Yoshihisa FUJISAKI ,  Kazuo ONO ,  Yoshitaka SASAGO

IPC分类号： H01L45/00 ,  H01L21/28

CPC分类号： H01L45/085 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/147 ,  H01L45/1625 ,  H01L45/1641

摘要： A solid electrolyte memory involves a problem that stable rewriting is difficult since the amount of ions in the solid electrolyte and the shape of the electrode are changed by repeating rewriting. In a semiconductor device in which information is stored or the circuit connection is changed by the change of resistance of the solid electrolyte layer, the solid electrolyte layer includes a composition, for example, of Cu—Ta—S and an ion supply layer in adjacent or close therewith as Cu—Ta—O, in which ions supplied from the ion supply layer form a conduction path in the solid electrolyte layer thereby making it possible to store information by the level of the resistance and applying the electric pulse to change the resistance, in which the ion supply layer includes crystals having, for example, a compositional ratio of: Cu—Ta—O=1:2:6 and rewriting operation can be performed stably.

摘要翻译： 固体电解质存储器存在难以稳定重写的问题，因为固体电解质中的离子量和电极的形状通过重复改写而改变。 在存储信息或通过固体电解质层的电阻变化来改变电路连接的半导体器件中，固体电解质层包括例如Cu-Ta-S的组合物和相邻的Cu-Ta-S的离子供给层 或与其接近的Cu-Ta-O，其中从离子供给层供给的离子在固体电解质层中形成传导路径，从而可以通过电阻水平存储信息并施加电脉冲以改变电阻 ，其中离子供给层包括例如以Cu-Ta-O = 1:2:6的组成比的晶体，并且可以稳定地进行重写操作。

公开(公告)号：US20090014708A1

公开(公告)日：2009-01-15

申请号：US12169818

申请日：2008-07-09

申请人： Yoshitaka SASAGO ,  Motoyasu Terao ,  Norikatsu Takaura ,  Yoshihisa Fujisaki ,  Tomoyuki Kodama ,  Nobuyuki Arasawa

发明人： Yoshitaka SASAGO ,  Motoyasu Terao ,  Norikatsu Takaura ,  Yoshihisa Fujisaki ,  Tomoyuki Kodama ,  Nobuyuki Arasawa

IPC分类号： H01L45/00

CPC分类号： H01L45/1206 ,  G06N3/063 ,  G11C13/0011 ,  H01L45/085 ,  H01L45/142 ,  H01L45/146 ,  H01L45/1675

摘要： A nonvolatile, sophisticated semiconductor device with a small surface area and a simple structure capable of switching connections between three or more electrodes. In a semiconductor device at least one of the electrodes contains atoms such as copper or silver in the solid electrolyte capable of easily moving within the solid electrolyte, and those electrodes face each other and applying a voltage switches the voltage on and off by generating or annihilating the conductive path between the electrodes. Moreover applying a voltage to a separate third electrode can annihilate the conductive path formed between two electrodes without applying a voltage to the two electrode joined by the conductive path.

摘要翻译： 具有小表面积的非易失性，复杂的半导体器件和能够切换三个或更多个电极之间的连接的简单结构。 在半导体器件中，电极中的至少一个在固体电解质中含有诸如铜或银之类的原子，能够容易地在固体电解质内移动，并且这些电极彼此面对并且施加电压通过产生或消除电压来开启和关闭电压 电极之间的导电路径。 此外，向单独的第三电极施加电压可以消除在两个电极之间形成的导电路径，而不向由导电路径连接的两个电极施加电压。

公开(公告)号：US20070257305A1

公开(公告)日：2007-11-08

申请号：US11740799

申请日：2007-04-26

申请人： Yoshitaka SASAGO ,  Tomoyuki Ishi ,  Toshiyuki Mine ,  Taro Osabe

发明人： Yoshitaka SASAGO ,  Tomoyuki Ishi ,  Toshiyuki Mine ,  Taro Osabe

IPC分类号： H01L29/788

CPC分类号： H01L27/115 ,  G11C16/0416 ,  G11C16/0483 ,  H01L21/764 ,  H01L27/11521 ,  H01L27/11524

摘要： By decreasing the threshold voltage shift due to the potential change of the cells adjacent in a word line direction, the reliability of a flash memory can be enhanced. Memory cells of a flash memory are formed in p-type wells of a semiconductor substrate and include gate insulator films, floating gates, high-K insulator films, and control gates (word lines). The floating gates and control gates (word lines) are isolated by high-K insulator films. The plurality of memory cells arrayed in row a direction are isolated by isolation trenches extending in a column direction. In the isolation trenches, a silicon oxide film is embedded. In the silicon oxide film, an air gap is provided. A lower end of the air gap extends near to the bottom of the isolation trench, and its upper end extends further above the upper surface of the high-K insulator film covering the floating gate.

摘要翻译： 通过由于在字线方向上相邻的单元的电位变化而减小阈值电压偏移，可以提高闪速存储器的可靠性。 闪存的存储单元形成在半导体衬底的p型阱中，并且包括栅绝缘膜，浮栅，高K绝缘膜和控制栅（字线）。 浮动栅极和控制栅极（字线）由高K绝缘膜隔离。 沿着一个方向排列的多个存储单元通过沿列方向延伸的隔离沟槽隔离。 在隔离沟槽中，嵌入氧化硅膜。 在氧化硅膜中设置气隙。 气隙的下端部靠近隔离沟槽的底部延伸，并且其上端进一步延伸到覆盖浮动栅极的高K绝缘膜的上表面上方。