公开(公告)号：US20160155732A1

公开(公告)日：2016-06-02

申请号：US15017397

申请日：2016-02-05

申请人： Marvell World Trade Ltd.

发明人： Albert Wu ,  Roawen Chen ,  Chung Chyung (Justin) Han ,  Shiann-Ming Liou ,  Chien-Chuan Wei ,  Runzi Chang ,  Scott Wu ,  Chuan-Cheng Cheng

IPC分类号： H01L25/00 ,  H01L21/48 ,  H01L21/56 ,  H01L25/065 ,  H01L23/498 ,  H01L21/768 ,  H01L23/00

CPC分类号： H01L25/04 ,  H01L21/486 ,  H01L21/565 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/13 ,  H01L23/147 ,  H01L23/3677 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L24/09 ,  H01L24/16 ,  H01L24/17 ,  H01L24/33 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/13024 ,  H01L2224/14181 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/81193 ,  H01L2224/83904 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/1515 ,  H01L2924/15153 ,  H01L2924/15156 ,  H01L2924/15159 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： Embodiments of the present disclosure provide an apparatus comprising a semiconductor substrate having a first surface, a second surface that is disposed opposite to the first surface, wherein at least a portion of the first surface is recessed to form a recessed region of the semiconductor substrate, and one or more vias formed in the recessed region of the semiconductor substrate to provide an electrical or thermal pathway between the first surface and the second surface of the semiconductor substrate, and a die coupled to the semiconductor substrate, the die being electrically coupled to the one or more vias formed in the recessed region of the semiconductor substrate. Other embodiments may be described and/or claimed.

摘要翻译： 本公开的实施例提供了一种装置，包括具有第一表面的半导体衬底，与第一表面相对设置的第二表面，其中第一表面的至少一部分被凹入以形成半导体衬底的凹陷区域， 以及形成在半导体衬底的凹陷区域中以在半导体衬底的第一表面和第二表面之间提供电或热路径的一个或多个通孔，以及耦合到半导体衬底的管芯，该管芯电耦合到 形成在半导体衬底的凹陷区域中的一个或多个通孔。 可以描述和/或要求保护其他实施例。

公开(公告)号：US20150194518A1

公开(公告)日：2015-07-09

申请号：US14567971

申请日：2014-12-11

申请人： Marvell World Trade Ltd.

发明人： Chuan-Cheng Cheng ,  Runzi Chang

IPC分类号： H01L29/78 ,  H01L29/66

CPC分类号： H01L29/785 ,  H01L29/4238 ,  H01L29/66795

摘要： Embodiments include a semiconductor device comprising: a gate layer comprising (i) a first section and (ii) a second section, wherein the gate layer is non-linear such that the first section of the gate layer is offset with respect to the second section of the gate layer; and a first contact and a second contact, wherein the first section of the gate layer is at (i) a first distance from the first contact and (ii) a second distance from the second contact, wherein the first distance is different from the second distance.

摘要翻译： 实施例包括半导体器件，包括：栅极层，包括（i）第一部分和（ii）第二部分，其中栅极层是非线性的，使得栅极层的第一部分相对于第二部分偏移 的栅层; 以及第一接触和第二接触，其中所述栅极层的所述第一部分处于（i）距离所述第一接触的第一距离和（ii）距所述第二接触的第二距离，其中所述第一距离与所述第二接触不同 距离。

公开(公告)号：US20140124961A1

公开(公告)日：2014-05-08

申请号：US14153892

申请日：2014-01-13

申请人： Marvell World Trade Ltd.

发明人： Albert WU ,  Roawen Chen ,  Chung Chyung Han ,  Shiann-Ming Liou ,  Chien-Chuan Wei ,  Runzi Chang ,  Scott Wu ,  Chuan-Cheng Cheng

IPC分类号： H01L25/04

CPC分类号： H01L25/04 ,  H01L21/486 ,  H01L21/565 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/13 ,  H01L23/147 ,  H01L23/3677 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L24/09 ,  H01L24/16 ,  H01L24/17 ,  H01L24/33 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/13024 ,  H01L2224/14181 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/81193 ,  H01L2224/83904 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/1515 ,  H01L2924/15153 ,  H01L2924/15156 ,  H01L2924/15159 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： Embodiments of the present disclosure provide a method comprising providing a semiconductor substrate having (i) a first surface and (ii) a second surface that is disposed opposite to the first surface, forming a dielectric film on the first surface of the semiconductor substrate, forming a redistribution layer on the dielectric film, electrically coupling one or more dies to the redistribution layer, forming a molding compound on the semiconductor substrate, recessing the second surface of the semiconductor substrate, forming one or more channels through the recessed second surface of the semiconductor substrate to expose the redistribution layer; and forming one or more package interconnect structures in the one or more channels, the one or more package interconnect structures being electrically coupled to the redistribution layer, the one or more package interconnect structures to route electrical signals of the one or more dies. Other embodiments may be described and/or claimed.

摘要翻译： 本公开的实施例提供了一种方法，包括提供具有（i）第一表面和（ii）与第一表面相对设置的第二表面的半导体衬底，在半导体衬底的第一表面上形成电介质膜，形成 电介质膜上的再分配层，将一个或多个管芯电耦合到再分布层，在半导体衬底上形成模制化合物，使半导体衬底的第二表面凹陷，通过半导体的凹陷的第二表面形成一个或多个沟道 衬底以暴露再分布层; 以及在所述一个或多个通道中形成一个或多个封装互连结构，所述一个或多个封装互连结构电耦合到所述再分布层，所述一个或多个封装互连结构用于布置所述一个或多个管芯的电信号。 可以描述和/或要求保护其他实施例。

公开(公告)号：US09275929B2

公开(公告)日：2016-03-01

申请号：US14678304

申请日：2015-04-03

申请人： Marvell World Trade Ltd.

发明人： Shiann-Ming Liou ,  Sehat Sutardja ,  Albert Wu ,  Chuan-Cheng Cheng ,  Chien-Chuan Wei

IPC分类号： H01L21/50 ,  H01L21/48 ,  H01L23/42 ,  H01L23/14 ,  H01L23/31 ,  H01L23/498 ,  H01L23/60 ,  H01L23/00 ,  H01L25/065

CPC分类号： H01L23/42 ,  H01L23/147 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/60 ,  H01L24/11 ,  H01L24/16 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12035 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15321 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： Embodiments of the present disclosure provide a method that includes providing a semiconductor substrate comprising a semiconductor material, forming a dielectric layer on the semiconductor substrate, forming an interconnect layer on the dielectric layer, attaching a semiconductor die to the semiconductor substrate, and electrically coupling an active side of the semiconductor die to the interconnect layer, the interconnect layer to route electrical signals of the semiconductor die. Other embodiments may be described and/or claimed.

摘要翻译： 本公开的实施例提供了一种方法，其包括提供包括半导体材料的半导体衬底，在半导体衬底上形成电介质层，在电介质层上形成互连层，将半导体管芯附着到半导体衬底上， 半导体管芯的有源侧到互连层，互连层以引导半导体管芯的电信号。 可以描述和/或要求保护其他实施例。

公开(公告)号：US20150155202A1

公开(公告)日：2015-06-04

申请号：US14613157

申请日：2015-02-03

申请人： Marvell World Trade Ltd.

发明人： Sehat Sutardja ,  Chung Chyung Han ,  Weidan Li ,  Shuhua Yu ,  Chuan-Cheng Cheng ,  Albert Wu

IPC分类号： H01L21/768 ,  H01L25/00 ,  H01L23/00

CPC分类号： H01L21/76885 ,  H01L23/3107 ,  H01L23/5226 ,  H01L23/5286 ,  H01L24/05 ,  H01L24/06 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/85 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/061 ,  H01L2224/16145 ,  H01L2224/16245 ,  H01L2224/45111 ,  H01L2224/45116 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48247 ,  H01L2224/48624 ,  H01L2224/48647 ,  H01L2224/48724 ,  H01L2224/48747 ,  H01L2224/48824 ,  H01L2224/48847 ,  H01L2224/731 ,  H01L2224/85 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： Embodiments of the present disclosure provide a chip that comprises a base metal layer formed over a first semiconductor die and a first metal layer formed over the base metal layer. The first metal layer includes a plurality of islands configured to route at least one of (i) a ground signal or (ii) a power signal in the chip. The chip further comprises a second metal layer formed over the first metal layer. The second metal layer includes a plurality of islands configured to route at least one of (i) the ground signal or (ii) the power signal in the chip.

摘要翻译： 本公开的实施例提供一种芯片，其包括形成在第一半导体管芯上的基底金属层和形成在基底金属层上的第一金属层。 第一金属层包括被配置为路由芯片中的（i）接地信号或（ii）功率信号中的至少一个的多个岛。 芯片还包括形成在第一金属层上的第二金属层。 第二金属层包括被配置为路由（i）接地信号或（ii）芯片中的功率信号中的至少一个的多个岛。

公开(公告)号：US10217669B2

公开(公告)日：2019-02-26

申请号：US15211256

申请日：2016-07-15

申请人： Marvell World Trade Ltd.

发明人： Runzi Chang ,  Chuan-Cheng Cheng

IPC分类号： H01L21/76 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L21/84 ,  H01L21/762 ,  H01L21/764 ,  H01L27/12 ,  H01L21/28

摘要： In an embodiment, a method comprises: forming a fin feature on a portion of a surface of a substrate; forming a first region of polycrystalline silicon over a first portion of the fin feature; forming a second region of polycrystalline silicon over a second portion of the fin feature; forming a third region of polycrystalline silicon over a third portion of the fin feature, wherein the third region of polycrystalline silicon is disposed between (i) the first region and (ii) the second region; forming a first spacer region between the first region and the third region; forming a second spacer region between the second region and the third region; removing the third region and at least a portion of the fin feature formed under the third region to thereby form a gap; and disposing a second dielectric material into the gap to form an isolation component.

公开(公告)号：US09768144B2

公开(公告)日：2017-09-19

申请号：US15017397

申请日：2016-02-05

申请人： Marvell World Trade Ltd.

发明人： Albert Wu ,  Roawen Chen ,  Chung Chyung (Justin) Han ,  Shiann-Ming Liou ,  Chien-Chuan Wei ,  Runzi Chang ,  Scott Wu ,  Chuan-Cheng Cheng

IPC分类号： H01L25/04 ,  H01L21/48 ,  H01L23/13 ,  H01L23/14 ,  H01L23/498 ,  H01L25/065 ,  H01L25/10 ,  H01L25/00 ,  H01L21/56 ,  H01L21/768 ,  H01L23/367 ,  H01L23/00

CPC分类号： H01L25/04 ,  H01L21/486 ,  H01L21/565 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/13 ,  H01L23/147 ,  H01L23/3677 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L24/09 ,  H01L24/16 ,  H01L24/17 ,  H01L24/33 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/13024 ,  H01L2224/14181 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/81193 ,  H01L2224/83904 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/1515 ,  H01L2924/15153 ,  H01L2924/15156 ,  H01L2924/15159 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： Embodiments of the present disclosure provide an apparatus comprising a semiconductor substrate having a first surface, a second surface that is disposed opposite to the first surface, wherein at least a portion of the first surface is recessed to form a recessed region of the semiconductor substrate, and one or more vias formed in the recessed region of the semiconductor substrate to provide an electrical or thermal pathway between the first surface and the second surface of the semiconductor substrate, and a die coupled to the semiconductor substrate, the die being electrically coupled to the one or more vias formed in the recessed region of the semiconductor substrate. Other embodiments may be described and/or claimed.

公开(公告)号：US20160329249A1

公开(公告)日：2016-11-10

申请号：US15211256

申请日：2016-07-15

申请人： Marvell World Trade Ltd.

发明人： Runzi Chang ,  Chuan-Cheng Cheng

IPC分类号： H01L21/8234 ,  H01L29/66 ,  H01L21/28 ,  H01L21/762

CPC分类号： H01L21/823431 ,  H01L21/28035 ,  H01L21/76224 ,  H01L21/764 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/66795

摘要： In an embodiment, a method comprises: forming a fin feature on a portion of a surface of a substrate; forming a first region of polycrystalline silicon over a first portion of the fin feature; forming a second region of polycrystalline silicon over a second portion of the fin feature; forming a third region of polycrystalline silicon over a third portion of the fin feature, wherein the third region of polycrystalline silicon is disposed between (i) the first region and (ii) the second region; forming a first spacer region between the first region and the third region; forming a second spacer region between the second region and the third region; removing the third region and at least a portion of the fin feature formed under the third region to thereby form a gap; and disposing a second dielectric material into the gap to form an isolation component.

摘要翻译： 在一个实施例中，一种方法包括：在衬底表面的一部分上形成翅片特征; 在所述翅片特征的第一部分上形成多晶硅的第一区域; 在鳍片特征的第二部分上形成多晶硅的第二区域; 在所述翅片特征的第三部分上形成多晶硅的第三区域，其中所述多晶硅的所述第三区域设置在（i）所述第一区域和（ii）所述第二区域之间; 在所述第一区域和所述第三区域之间形成第一间隔区域; 在所述第二区域和所述第三区域之间形成第二间隔区域; 去除第三区域和形成在第三区域下方的翅片特征的至少一部分，从而形成间隙; 以及将第二电介质材料设置在间隙中以形成隔离部件。

公开(公告)号：US20190148236A1

公开(公告)日：2019-05-16

申请号：US16230505

申请日：2018-12-21

申请人： Marvell World Trade Ltd.

发明人： Runzi Chang ,  Chuan-Cheng Cheng

IPC分类号： H01L21/8234 ,  H01L21/28 ,  H01L27/12 ,  H01L21/764 ,  H01L29/66 ,  H01L21/84 ,  H01L27/088 ,  H01L21/762

CPC分类号： H01L21/823431 ,  H01L21/28035 ,  H01L21/76224 ,  H01L21/764 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/66795

摘要： In an embodiment, a method comprises: forming a fin feature on a portion of a surface of a substrate; forming a first region of polycrystalline silicon over a first portion of the fin feature; forming a second region of polycrystalline silicon over a second portion of the fin feature; forming a third region of polycrystalline silicon over a third portion of the fin feature, wherein the third region of polycrystalline silicon is disposed between (i) the first region and (ii) the second region; forming a first spacer region between the first region and the third region; forming a second spacer region between the second region and the third region; removing the third region and at least a portion of the fin feature formed under the third region to thereby form a gap; and disposing a second dielectric material into the gap to form an isolation component.

公开(公告)号：US09397218B2

公开(公告)日：2016-07-19

申请号：US14567971

申请日：2014-12-11

申请人： Marvell World Trade Ltd.

发明人： Chuan-Cheng Cheng ,  Runzi Chang

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/423

CPC分类号： H01L29/785 ,  H01L29/4238 ,  H01L29/66795

摘要： Embodiments include a semiconductor device comprising: a gate layer comprising (i) a first section and (ii) a second section, wherein the gate layer is non-linear such that the first section of the gate layer is offset with respect to the second section of the gate layer; and a first contact and a second contact, wherein the first section of the gate layer is at (i) a first distance from the first contact and (ii) a second distance from the second contact, wherein the first distance is different from the second distance.

摘要翻译： 实施例包括半导体器件，包括：栅极层，包括（i）第一部分和（ii）第二部分，其中栅极层是非线性的，使得栅极层的第一部分相对于第二部分偏移 的栅层; 以及第一接触和第二接触，其中所述栅极层的所述第一部分处于（i）距离所述第一接触的第一距离和（ii）距所述第二接触的第二距离，其中所述第一距离与所述第二接触不同 距离。