公开(公告)号：US06205560B1

公开(公告)日：2001-03-20

申请号：US08606769

申请日：1996-02-27

Applicant: Mark W. Hervin ,  Mark W. Bluhm ,  Stanley D. Harder ,  William C. Patton

Inventor： Mark W. Hervin ,  Mark W. Bluhm ,  Stanley D. Harder ,  William C. Patton

IPC: H02H305

CPC classification number: G06F11/2236 ,  G06F11/3656

Abstract: A circuit for diagnosing and debugging a processor for executing a stream of instructions that includes a set of debug registers for identifying an instruction or data address breakpoint; a processor for generating a debug exception in response to an instruction or data address in the stream of instructions matching the instruction or data breakpoint stored in the set of debug registers and a debug configuration register for enabling transfer of program control to one of a plurality of destinations in response to the debug exception. The debug configuration registers may designate system management mode, JTAG routine or a software debug interrupt handler as the destination.

Abstract translation: 一种用于诊断和调试处理器的电路，用于执行包括用于识别指令或数据地址断点的一组调试寄存器的指令流; 用于响应于与存储在所述一组调试寄存器中的指令或数据断点相匹配的指令流中的指令或数据地址产生调试异常的处理器和用于使程序控制能够传送到多个 响应调试异常的目的地。 调试配置寄存器可以指定系统管理模式，JTAG程序或软件调试中断处理程序作为目标。

公开(公告)号：US5838897A

公开(公告)日：1998-11-17

申请号：US606774

申请日：1996-02-27

Applicant: Mark W. Bluhm ,  Mark W. Hervin

Inventor： Mark W. Bluhm ,  Mark W. Hervin

IPC: G06F11/267 ,  G06F11/36 ,  G06F11/00

CPC classification number: G06F11/2236 ,  G06F11/3656

Abstract: A processor for outputting processor state information during idle bus cycles to facilitate the diagnosing and debugging of a processor. The processor includes a plurality of external pins for communicating data from the processor; a visibility register for selecting one of a plurality of modes which identifies processor state information to output onto the plurality of external pins; and a bus interface unit for communicating data to the external pins of the processor and for detecting an idle bus cycle. The bus interface unit outputs processor state information according to the identified mode onto the plurality of external pins in response to detecting an idle bus cycle.

Abstract translation: 一种用于在空闲总线周期期间输出处理器状态信息以便于诊断和调试处理器的处理器。 处理器包括用于从处理器传送数据的多个外部引脚; 可见度寄存器，用于选择识别处理器状态信息以输出到所述多个外部引脚上的多个模式之一; 以及用于将数据传送到处理器的外部引脚并用于检测空闲总线周期的总线接口单元。 响应于检测到空闲总线周期，总线接口单元根据识别的模式向多个外部引脚输出处理器状态信息。

公开(公告)号：US5644741A

公开(公告)日：1997-07-01

申请号：US138855

申请日：1993-10-18

Applicant: Mark W. Bluhm ,  Mark W. Hervin ,  Steven C. McMahan ,  Raul A. Garibay, Jr.

Inventor： Mark W. Bluhm ,  Mark W. Hervin ,  Steven C. McMahan ,  Raul A. Garibay, Jr.

IPC: G06F9/26 ,  G06F9/28 ,  G06F9/30 ,  G06F9/22

CPC classification number: G06F9/265 ,  G06F9/28 ,  G06F9/30145

Abstract: A processor includes storage circuitry for storing an instruction and memory circuitry addressable by a microaddress for outputting a microinstruction in response to the microaddress. The processor further includes sequencing circuitry coupled to provide the microaddress to the memory circuitry. Finally, the processor includes decode circuitry coupled to the storage circuitry for detecting whether the instruction stored in the storage circuitry comprises a single clock instruction before the memory circuit outputs the microinstruction, and for indicating to the sequencing circuitry in response to detecting whether the instruction stored in the storage circuitry comprises a single clock instruction.

Abstract translation: 处理器包括存储电路，用于存储可由微地址寻址的指令和存储器电路，用于响应于微地址输出微指令。 处理器还包括被连接以向存储器电路提供微地址的排序电路。 最后，处理器包括耦合到存储电路的解码电路，用于检测存储在存储电路中的指令是否在存储器电路输出微指令之前包括单个时钟指令，并且响应于检测指令是否存储 在存储电路中包括单个时钟指令。

公开(公告)号：US5963984A

公开(公告)日：1999-10-05

申请号：US857300

申请日：1997-05-16

Applicant: Raul A. Garibay, Jr. ,  Marc A. Quattromani ,  Douglas Beard ,  Mark W. Bluhm

Inventor： Raul A. Garibay, Jr. ,  Marc A. Quattromani ,  Douglas Beard ,  Mark W. Bluhm

IPC: G06F12/10 ,  G06F12/00

CPC classification number: G06F12/1027 ,  G06F2212/651 ,  G06F2212/652 ,  G06F2212/681

Abstract: Systems and methods for virtual addressing are disclosed having an address translation unit with variable page size by employing direct, victim, and programmable block translation look aside buffers. Selective comparisons between contents on a linear address bus and linear address tags are controlled by a size mask register which further controls a multiplexer to selectively steer bits onto a physical address bus from either the linear address bus or a physical address register.

Abstract translation: 公开了用于虚拟寻址的系统和方法，其具有通过采用直接的，受害的和可编程的块翻译放置缓冲器的具有可变页面大小的地址转换单元。 线性地址总线和线性地址标签上的内容之间的选择性比较由大小屏蔽寄存器控制，该大小屏蔽寄存器进一步控制多路复用器以选择性地将位从线性地址总线或物理地址寄存器转向物理地址总线。

公开(公告)号：US5664149A

公开(公告)日：1997-09-02

申请号：US151489

申请日：1993-11-12

Applicant: Marvin Wayne Martinez, Jr. ,  Mark W. Bluhm ,  Jeffrey S. Byrne ,  David A. Courtright ,  Douglas Ewing Duschatko ,  Raul A. Garibay, Jr. ,  Margaret R. Herubin

Inventor： Marvin Wayne Martinez, Jr. ,  Mark W. Bluhm ,  Jeffrey S. Byrne ,  David A. Courtright ,  Douglas Ewing Duschatko ,  Raul A. Garibay, Jr. ,  Margaret R. Herubin

IPC: G06F12/08 ,  G06F12/12 ,  G06F12/00

CPC classification number: G06F12/0804 ,  G06F12/0808 ,  G06F12/0831 ,  G06F12/0835

Abstract: A write-back coherency system, including FLUSH/INVAL and LOCK protocols, is used, in an exemplary embodiment, in a microprocessor used in a computer system that selectively provides to the processor FLUSH and INVAL signals to implement a limited write-back protocol. The FLUSH/INVAL protocol is used by the computer system to control export and invalidate operations. In response to a FLUSH signal, the microprocessor exports dirty data from the cache. If INVAL is also asserted, the cache is also invalidated (i.e., if FLUSH is asserted and INVAL is not asserted, no invalidation is performed). With the LOCK protocol, LOCKed reads are serviced out of the cache for read hits--however, to maintain compatibility with computer systems that expect a LOCK operation to involve a read followed by a write access to external memory, the microprocessor will still run the external LOCKed read cycle, ignoring the returned data.

Abstract translation: 在示例性实施例中，在计算机系统中使用的微处理器中使用包括FLUSH / INVAL和LOCK协议的回写一致性系统，其选择性地向处理器提供FLUSH和INVAL信号以实现有限的回写协议。 计算机系统使用FLUSH / INVAL协议来控制导出和无效操作。 响应于FLUSH信号，微处理器从缓存中导出脏数据。 如果INVAL也被置位，则高速缓存也被无效（即，如果FLUSH被断言且INVAL未被置位，则不执行无效）。 使用LOCK协议，LOCK读取从高速缓存中进行读取命中，但是为了保持与计算机系统的兼容性，这些计算机系统期望LOCK操作涉及读取，然后对外部存储器进行写访问，微处理器仍然会运行外部 锁定的读取周期，忽略返回的数据。

公开(公告)号：US5937178A

公开(公告)日：1999-08-10

申请号：US906859

申请日：1997-08-06

Applicant: Mark W. Bluhm

Inventor： Mark W. Bluhm

IPC: G06F9/30 ,  G06F12/04

CPC classification number: G06F9/30141 ,  G06F9/30109 ,  G06F9/384

Abstract: A microprocessor includes an execution unit for processing a stream of instructions wherein one or more of the instructions reference the eight logical x86 general purpose registers as source and destination registers for operands for the instructions. The microprocessor further includes a register file with a plurality of physical registers in excess of the eight x86 general purpose registers. The physical registers in the register file are mapped to the logical x86 general purpose registers such that one of the physical registers may contain one or more logical source or destination registers of the x86 general purpose registers for an instruction. The register file drives the entire bits of the physical register which contains the destination register for the instruction onto an internal bus. The bits are stored in a latching circuit in the register file. The execution unit performs the instruction and returns the resulting operand to be stored in the logical destination register. A multiplexing circuit then overwrites the bits in the physical register corresponding to the logical destination register with the resulting operand. The bits of the physical register are then written back to the physical registers.

Abstract translation: 微处理器包括用于处理指令流的执行单元，其中一个或多个指令引用八个逻辑x86通用寄存器作为用于指令的操作数的源寄存器和目标寄存器。 微处理器还包括具有超过八个x86通用寄存器的多个物理寄存器的寄存器文件。 寄存器文件中的物理寄存器被映射到逻辑x86通用寄存器，使得一个物理寄存器可以包含用于指令的x86通用寄存器的一个或多个逻辑源或目标寄存器。 寄存器文件将包含目标寄存器的物理寄存器的整个位驱动到内部总线上。 这些位存储在寄存器文件中的锁存电路中。 执行单元执行指令并返回所存储的逻辑目标寄存器中的操作数。 然后，多路复用电路将与对应于逻辑目的地寄存器的物理寄存器中的比特重写为结果操作数。 然后物理寄存器的位被写回物理寄存器。

公开(公告)号：US5898815A

公开(公告)日：1999-04-27

申请号：US600781

申请日：1996-02-13

Applicant: Mark W. Bluhm ,  Marvin W. Martinez, Jr.

Inventor： Mark W. Bluhm ,  Marvin W. Martinez, Jr.

IPC: G06F13/42 ,  G06F13/372

CPC classification number: G06F13/4226

Abstract: A bus interface unit of a processor comprises an I/O recovery counter for preventing peripheral overrun due to successive I/O bus cycles. The I/O recovery counter counts the necessary I/O recovery period between I/O bus cycles necessary to prevent peripheral overrun. The I/O recovery counter comprises a clock input from the processor and a signal derived from the bus control signal READY. The I/O recovery counter begins to count at the receipt of the READY signal after the initiation of an I/O bus cycle. The bus interface unit waits until the I/O recovery counter completes its count of the I/O recovery period prior to initiating another I/O bus cycle.

Abstract translation: 处理器的总线接口单元包括I / O恢复计数器，用于防止由于连续的I / O总线周期引起的外围超载。 I / O恢复计数器可以计算防止外设溢出所必需的I / O总线周期之间的必要I / O恢复周期。 I / O恢复计数器包括来自处理器的时钟输入和从总线控制信号READY得到的信号。 在I / O总线周期开始之后，I / O恢复计数器开始计数。 总线接口单元等待，直到I / O恢复计数器在启动另一个I / O总线周期之前完成I / O恢复周期的计数。

公开(公告)号：US5784589A

公开(公告)日：1998-07-21

申请号：US607567

申请日：1996-02-27

Applicant: Mark W. Bluhm

Inventor： Mark W. Bluhm

IPC: G06F9/312 ,  G06F9/38

CPC classification number: G06F9/30043 ,  G06F9/3824 ,  G06F9/383 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3853 ,  G06F9/3857 ,  G06F9/3867 ,  G06F9/3875

Abstract: In a pipelined processor having at least one execution pipeline for executing instructions, the execution pipeline including ID (decode), AC (address calculation), and EX (execution) processing stages to process instructions for the processor, the processor including a register translation system that controls a renaming of physical registers of the processor to logical registers thereof, a tracking circuit that tracks availability of the physical registers for the renaming, method of operation thereof and processor containing the same. The tracking circuit includes: (1) ID, AC and EX tracking registers corresponding to the ID, AC and EX processing stages, each of the ID, AC and EX tracking registers containing tracking indicators corresponding to physical registers of the processor to be tracked, (2) read detection circuitry that changes a particular tracking indicator of a particular tracking register from a "not-read" state to a "read" state when an instruction being processed in a particular processing stage corresponding to the particular tracking register causes the particular processing stage to read a value from a particular physical register corresponding to the particular tracking indicator and (3) combinatorial circuitry that designates the particular physical register as available for the renaming only when all particular tracking indicators of the ID, AC and EX tracking registers corresponding to the particular physical register are in the "not-read" state.

Abstract translation: 在具有用于执行指令的至少一个执行流水线的流水线处理器中，执行流水线包括ID（解码），AC（地址计算）和EX（执行）处理阶段，以处理处理器的指令，处理器包括寄存器转换系统 其控制将处理器的物理寄存器重命名为其逻辑寄存器，跟踪电路，跟踪用于重命名的物理寄存器的可用性，其操作方法和包含该物理寄存器的处理器。 跟踪电路包括：（1）对应于ID，AC和EX处理级的ID，AC和EX跟踪寄存器，ID，AC和EX跟踪寄存器中的每一个包括与要跟踪的处理器的物理寄存器对应的跟踪指示符， （2）当在与特定跟踪寄存器相对应的特定处理阶段中处理的指令导致特定跟踪寄存器的特定跟踪指示符将特定跟踪寄存器从“未读”状态改变为“读”状态时， 处理阶段，以从特定的跟踪指示器对应的特定物理寄存器读取值;以及（3）仅当ID，AC和EX跟踪寄存器的所有特定跟踪指示符对应的组合电路才将该特定物理寄存器指定为可用于重命名 特定物理寄存器处于“未读”状态。

公开(公告)号：US5771365A

公开(公告)日：1998-06-23

申请号：US396857

申请日：1995-03-01

Applicant: Steven C. McMahan ,  Mark W. Bluhm

Inventor： Steven C. McMahan ,  Mark W. Bluhm

IPC: G06F9/38 ,  G06F9/26 ,  G06F9/28 ,  G06F9/30 ,  G06F9/32 ,  G06F12/02

CPC classification number: G06F9/30167 ,  G06F9/261 ,  G06F9/265 ,  G06F9/28 ,  G06F9/30145

Abstract: A microarchitecture in a complex instruction computer system is disclosed employing a sparse microROM array and concatenation address circuitry for forming microaddress entry points, avoiding the need for a programmable logic array to translate instruction opcodes and avoiding duplicative entry points, thus minimizing the microROM array size.

Abstract translation: 公开了一种复杂指令计算机系统中的微架构，其使用用于形成微地址入口点的稀疏微阵列和级联地址电路，避免了对可编程逻辑阵列转换指令操作码并避免重复入口点的需要，从而使微ROM阵列尺寸最小化。

公开(公告)号：US5596731A

公开(公告)日：1997-01-21

申请号：US426300

申请日：1995-04-21

Applicant: Marvin W. Martinez, Jr. ,  Mark W. Bluhm

Inventor： Marvin W. Martinez, Jr. ,  Mark W. Bluhm

IPC: G06F12/08 ,  G06F13/38

CPC classification number: G06F12/0897

Abstract: A single block bus transfer (SCBT) protocol is implemented, in an exemplary embodiment, in a computer system that includes an .times.86 microprocessor, system logic, and an external memory subsystem including L2 cache and system DRAM, intercoupled by a 586 bus architecture. The microprocessor's bus interface unit (BIU) includes SCBT logic that generates internal effective BRDY# and the effective KEN# signals from either (a) L2.sub.-- HIT from the L2 cache, or (b) BRDY# or KEN# from the system logic. The effective KEN# signal is used for convert a potentially cacheable read into a burst fill cycle. The exemplary L2 cache is able to perform address decode and cache look-up in time to return L2 HIT to the processor during the ADS# clock with sufficient timing margin to permit the processor to complete the bus transfer (either not burst bus cycle, or the first bus transfer of a burst cycle) in that clock and set up for a next bus transfer in the next clock. The BIU uses a forced deadclock mechanism to prevent a single clock bus transfer from being followed in the next clock by a next bus transfer if the result would be consecutive read and write cycles (thereby avoiding device driver contention on the data bus).

Abstract translation: 在示例性实施例中，在包括由586总线架构相互耦合的x86微处理器，系统逻辑和包括L2高速缓存和系统DRAM的外部存储器子系统的计算机系统中实现单块总线传送（SCBT）协议。 微处理器的总线接口单元（BIU）包括产生内部有效BRDY＃的SCBT逻辑和来自L2缓存的（a）L2-HIT的有效KEN＃信号，或（b）来自系统逻辑的BRDY＃或KEN＃。 有效的KEN＃信号用于将潜在的可缓存读取转换为突发填充周期。 示例性L2高速缓存能够在ADS＃时钟期间及时地执行地址解码和高速缓存查找以在ADS＃时钟期间将L2 HIT返回到处理器，以允许处理器完成总线传输（不是突发总线周期或 在该时钟中的第一个总线传输突发周期），并在下一个时钟设置下一个总线传输。 如果结果将是连续的读和写周期（从而避免数据总线上的设备驱动程序争用），BIU使用强制死锁机制来防止在下一个时钟中通过下一个总线传输来跟踪单个时钟总线传输。