公开(公告)号：US09256548B2

公开(公告)日：2016-02-09

申请号：US13688520

申请日：2012-11-29

Applicant: Donald Edward Steiss ,  Marvin Wayne Martinez, Jr. ,  John H. W. Bettink ,  John C. Carney ,  Mark Warden Hervin

Inventor： Donald Edward Steiss ,  Marvin Wayne Martinez, Jr. ,  John H. W. Bettink ,  John C. Carney ,  Mark Warden Hervin

IPC: G06F12/00 ,  G06F12/10

CPC classification number: G06F12/1009

Abstract: In one embodiment, rule-based virtual address translation is performed for accessing data (e.g., reading and/or writing data) typically stored in different manners and/or locations among one or more memories, such as, but not limited to, in packet switching devices. A virtual address is matched against a set of predetermined rules to identify one or more storing description parameters. These storing description parameters determine in which particular memory unit(s) and/or how the data is stored. Thus, different portions of a data structure (e.g., table) can be stored in different memories and/or using different storage techniques. The virtual address is converted to a lookup address based on the identified storing description parameter(s). One or more read or write operations in one or more particular memory units is performed based on the lookup address said converted from the virtual address.

Abstract translation: 在一个实施例中，执行基于规则的虚拟地址转换，以访问通常以一个或多个存储器中的不同方式和/或位置存储的数据（例如，读取和/或写入数据），例如但不限于分组 开关器件。 将虚拟地址与一组预定规则进行匹配以识别一个或多个存储描述参数。 这些存储描述参数确定在哪个特定的存储器单元和/或如何存储数据。 因此，数据结构（例如，表）的不同部分可以存储在不同的存储器中和/或使用不同的存储技术。 基于所识别的存储描述参数将虚拟地址转换为查找地址。 基于从虚拟地址转换的查找地址来执行一个或多个特定存储器单元中的一个或多个读取或写入操作。

公开(公告)号：US20140149712A1

公开(公告)日：2014-05-29

申请号：US13688520

申请日：2012-11-29

Applicant: Donald Edward Steiss ,  Marvin Wayne Martinez, JR. ,  John H. W. Bettink ,  John C. Carney ,  Mark Warden Hervin

Inventor： Donald Edward Steiss ,  Marvin Wayne Martinez, JR. ,  John H. W. Bettink ,  John C. Carney ,  Mark Warden Hervin

IPC: G06F12/10

CPC classification number: G06F12/1009

Abstract: In one embodiment, rule-based virtual address translation is performed for accessing data (e.g., reading and/or writing data) typically stored in different manners and/or locations among one or more memories, such as, but not limited to, in packet switching devices. A virtual address is matched against a set of predetermined rules to identify one or more storing description parameters. These storing description parameters determine in which particular memory unit(s) and/or how the data is stored. Thus, different portions of a data structure (e.g., table) can be stored in different memories and/or using different storage techniques. The virtual address is converted to a lookup address based on the identified storing description parameter(s). One or more read or write operations in one or more particular memory units is performed based on the lookup address said converted from the virtual address.

Abstract translation: 在一个实施例中，执行基于规则的虚拟地址转换，以访问通常以一个或多个存储器中的不同方式和/或位置存储的数据（例如，读取和/或写入数据），例如但不限于分组 开关器件。 将虚拟地址与一组预定规则进行匹配以识别一个或多个存储描述参数。 这些存储描述参数确定在哪个特定的存储器单元和/或如何存储数据。 因此，数据结构（例如，表）的不同部分可以存储在不同的存储器中和/或使用不同的存储技术。 基于所识别的存储描述参数将虚拟地址转换为查找地址。 基于从虚拟地址转换的查找地址来执行一个或多个特定存储器单元中的一个或多个读取或写入操作。

公开(公告)号：US5664149A

公开(公告)日：1997-09-02

申请号：US151489

申请日：1993-11-12

Applicant: Marvin Wayne Martinez, Jr. ,  Mark W. Bluhm ,  Jeffrey S. Byrne ,  David A. Courtright ,  Douglas Ewing Duschatko ,  Raul A. Garibay, Jr. ,  Margaret R. Herubin

Inventor： Marvin Wayne Martinez, Jr. ,  Mark W. Bluhm ,  Jeffrey S. Byrne ,  David A. Courtright ,  Douglas Ewing Duschatko ,  Raul A. Garibay, Jr. ,  Margaret R. Herubin

IPC: G06F12/08 ,  G06F12/12 ,  G06F12/00

CPC classification number: G06F12/0804 ,  G06F12/0808 ,  G06F12/0831 ,  G06F12/0835

Abstract: A write-back coherency system, including FLUSH/INVAL and LOCK protocols, is used, in an exemplary embodiment, in a microprocessor used in a computer system that selectively provides to the processor FLUSH and INVAL signals to implement a limited write-back protocol. The FLUSH/INVAL protocol is used by the computer system to control export and invalidate operations. In response to a FLUSH signal, the microprocessor exports dirty data from the cache. If INVAL is also asserted, the cache is also invalidated (i.e., if FLUSH is asserted and INVAL is not asserted, no invalidation is performed). With the LOCK protocol, LOCKed reads are serviced out of the cache for read hits--however, to maintain compatibility with computer systems that expect a LOCK operation to involve a read followed by a write access to external memory, the microprocessor will still run the external LOCKed read cycle, ignoring the returned data.

Abstract translation: 在示例性实施例中，在计算机系统中使用的微处理器中使用包括FLUSH / INVAL和LOCK协议的回写一致性系统，其选择性地向处理器提供FLUSH和INVAL信号以实现有限的回写协议。 计算机系统使用FLUSH / INVAL协议来控制导出和无效操作。 响应于FLUSH信号，微处理器从缓存中导出脏数据。 如果INVAL也被置位，则高速缓存也被无效（即，如果FLUSH被断言且INVAL未被置位，则不执行无效）。 使用LOCK协议，LOCK读取从高速缓存中进行读取命中，但是为了保持与计算机系统的兼容性，这些计算机系统期望LOCK操作涉及读取，然后对外部存储器进行写访问，微处理器仍然会运行外部 锁定的读取周期，忽略返回的数据。

公开(公告)号：US5860111A

公开(公告)日：1999-01-12

申请号：US496712

申请日：1995-06-29

Applicant: Marvin Wayne Martinez, Jr. ,  Mark Bluhm ,  Jeffrey S. Byrne ,  David A. Courtright ,  Douglas Ewing Duschatko ,  Raul A. Garibay, Jr. ,  Margaret R. Herubin

Inventor： Marvin Wayne Martinez, Jr. ,  Mark Bluhm ,  Jeffrey S. Byrne ,  David A. Courtright ,  Douglas Ewing Duschatko ,  Raul A. Garibay, Jr. ,  Margaret R. Herubin

IPC: G06F12/08 ,  G06F12/12

CPC classification number: G06F12/0804 ,  G06F12/0808 ,  G06F12/0831 ,  G06F12/0835

Abstract: A write-back coherency system is used, in an exemplary embodiment, to implement write-back caching in an x86 processor installed in a multi-master computer system that does not support a write-back protocol for maintaining coherency between an internal cache and main memory during DMA operations. The write-back coherency system interrupts the normal bus arbitration operation to allow export of dirty data. In response to an arbitration-request (such as HOLD), if the internal cache contains dirty data, the processor is inhibited from providing arbitration-acknowledge (such as HLDA) until the dirty data is exported (the cache is dynamically switched to write-through mode to prevent data in the cache from being made dirty while the bus is arbitrated away). While the requesting bus master is accessing memory, bus snooping is performed and invalidation logic invalidates at least those cache locations corresponding to locations in memory that are affected by the requesting bus master.

Abstract translation: 在示例性实施例中，使用回写一致性系统来实现在安装在多主计算机系统中的x86处理器中的回写高速缓存，该多主计算机系统不支持用于维持内部高速缓存与主机之间的一致性的回写协议 DMA操作期间的内存。 回写一致性系统中断正常总线仲裁操作，以允许导出脏数据。 响应仲裁请求（如HOLD），如果内部缓存包含脏数据，则禁止处理器提供仲裁确认（例如HLDA），直到导出脏数据（高速缓存被动态切换为写入 - 通过模式来防止缓存中的数据在总线被仲裁时被弄脏）。 当请求总线主机访问存储器时，执行总线监听，并且无效逻辑至少对应于受请求总线主机影响的存储器中的位置的那些高速缓存位置无效。