公开(公告)号：US5664149A

公开(公告)日：1997-09-02

申请号：US151489

申请日：1993-11-12

Applicant: Marvin Wayne Martinez, Jr. ,  Mark W. Bluhm ,  Jeffrey S. Byrne ,  David A. Courtright ,  Douglas Ewing Duschatko ,  Raul A. Garibay, Jr. ,  Margaret R. Herubin

Inventor： Marvin Wayne Martinez, Jr. ,  Mark W. Bluhm ,  Jeffrey S. Byrne ,  David A. Courtright ,  Douglas Ewing Duschatko ,  Raul A. Garibay, Jr. ,  Margaret R. Herubin

IPC: G06F12/08 ,  G06F12/12 ,  G06F12/00

CPC classification number: G06F12/0804 ,  G06F12/0808 ,  G06F12/0831 ,  G06F12/0835

Abstract: A write-back coherency system, including FLUSH/INVAL and LOCK protocols, is used, in an exemplary embodiment, in a microprocessor used in a computer system that selectively provides to the processor FLUSH and INVAL signals to implement a limited write-back protocol. The FLUSH/INVAL protocol is used by the computer system to control export and invalidate operations. In response to a FLUSH signal, the microprocessor exports dirty data from the cache. If INVAL is also asserted, the cache is also invalidated (i.e., if FLUSH is asserted and INVAL is not asserted, no invalidation is performed). With the LOCK protocol, LOCKed reads are serviced out of the cache for read hits--however, to maintain compatibility with computer systems that expect a LOCK operation to involve a read followed by a write access to external memory, the microprocessor will still run the external LOCKed read cycle, ignoring the returned data.

Abstract translation: 在示例性实施例中，在计算机系统中使用的微处理器中使用包括FLUSH / INVAL和LOCK协议的回写一致性系统，其选择性地向处理器提供FLUSH和INVAL信号以实现有限的回写协议。 计算机系统使用FLUSH / INVAL协议来控制导出和无效操作。 响应于FLUSH信号，微处理器从缓存中导出脏数据。 如果INVAL也被置位，则高速缓存也被无效（即，如果FLUSH被断言且INVAL未被置位，则不执行无效）。 使用LOCK协议，LOCK读取从高速缓存中进行读取命中，但是为了保持与计算机系统的兼容性，这些计算机系统期望LOCK操作涉及读取，然后对外部存储器进行写访问，微处理器仍然会运行外部 锁定的读取周期，忽略返回的数据。

公开(公告)号：US5860111A

公开(公告)日：1999-01-12

申请号：US496712

申请日：1995-06-29

Applicant: Marvin Wayne Martinez, Jr. ,  Mark Bluhm ,  Jeffrey S. Byrne ,  David A. Courtright ,  Douglas Ewing Duschatko ,  Raul A. Garibay, Jr. ,  Margaret R. Herubin

Inventor： Marvin Wayne Martinez, Jr. ,  Mark Bluhm ,  Jeffrey S. Byrne ,  David A. Courtright ,  Douglas Ewing Duschatko ,  Raul A. Garibay, Jr. ,  Margaret R. Herubin

IPC: G06F12/08 ,  G06F12/12

CPC classification number: G06F12/0804 ,  G06F12/0808 ,  G06F12/0831 ,  G06F12/0835

Abstract: A write-back coherency system is used, in an exemplary embodiment, to implement write-back caching in an x86 processor installed in a multi-master computer system that does not support a write-back protocol for maintaining coherency between an internal cache and main memory during DMA operations. The write-back coherency system interrupts the normal bus arbitration operation to allow export of dirty data. In response to an arbitration-request (such as HOLD), if the internal cache contains dirty data, the processor is inhibited from providing arbitration-acknowledge (such as HLDA) until the dirty data is exported (the cache is dynamically switched to write-through mode to prevent data in the cache from being made dirty while the bus is arbitrated away). While the requesting bus master is accessing memory, bus snooping is performed and invalidation logic invalidates at least those cache locations corresponding to locations in memory that are affected by the requesting bus master.

Abstract translation: 在示例性实施例中，使用回写一致性系统来实现在安装在多主计算机系统中的x86处理器中的回写高速缓存，该多主计算机系统不支持用于维持内部高速缓存与主机之间的一致性的回写协议 DMA操作期间的内存。 回写一致性系统中断正常总线仲裁操作，以允许导出脏数据。 响应仲裁请求（如HOLD），如果内部缓存包含脏数据，则禁止处理器提供仲裁确认（例如HLDA），直到导出脏数据（高速缓存被动态切换为写入 - 通过模式来防止缓存中的数据在总线被仲裁时被弄脏）。 当请求总线主机访问存储器时，执行总线监听，并且无效逻辑至少对应于受请求总线主机影响的存储器中的位置的那些高速缓存位置无效。

公开(公告)号：US5878269A

公开(公告)日：1999-03-02

申请号：US859347

申请日：1992-03-27

Applicant: John K. Eitrheim ,  Richard B. Reis ,  Steve McMahan ,  Lawrence H. Hudepohl ,  Douglas Ewing Duschatko ,  Tai Dinh Ngo ,  Jeffrey Byrne

Inventor： John K. Eitrheim ,  Richard B. Reis ,  Steve McMahan ,  Lawrence H. Hudepohl ,  Douglas Ewing Duschatko ,  Tai Dinh Ngo ,  Jeffrey Byrne

IPC: H03K19/017 ,  G06F9/00

CPC classification number: H03K19/01707

Abstract: A microprocessor is implemented using sense amplifiers to replace CMOS logic circuits, in order to provide low voltage, high frequency switching. The input node of the sense amplifier is maintained at a voltage just above or just below their trip-point of one inverter in order to obtain high-speed switching. Bench mark tests have shown that a microprocessor operating at 2.7 volts may obtain a frequency of 20 MHz and while the same microprocessor may operate at 5.5 volts and 40 MHz.

Abstract translation: 使用读出放大器来实现微处理器来代替CMOS逻辑电路，以便提供低电压，高频率的切换。 读出放大器的输入节点保持在刚好高于或刚好低于其一个逆变器的跳变点的电压，以便获得高速切换。 台式标记测试表明，以2.7伏工作的微处理器可以获得20MHz的频率，同时微处理器可以工作在5.5伏和40MHz。

公开(公告)号：US5644788A

公开(公告)日：1997-07-01

申请号：US330402

申请日：1994-10-28

Applicant: David A. Courtright ,  Douglas Ewing Duschatko

Inventor： David A. Courtright ,  Douglas Ewing Duschatko

IPC: G06F13/28

CPC classification number: G06F13/28

Abstract: Burst ordering logic is used, in an exemplary embodiment, to implement an ascending only burst ordering for cache line fills in 486 computer systems while maintaining compatibility with the conventional 486 burst ordering which uses both ascending and descending burst orders depending upon the position of the requested address (critical Dword) within a cache line (conventional 486 burst ordering is illustrated in Table 1 in the Background). The burst ordering logic (60) implements a 1+4 burst ordering for requested addresses that, for conventional 486 burst ordering, would result in a descending burst order (the exemplary 1+4 burst ordering is illustrated in Table 2 in the Specification). The burst ordering logic includes request modification circuitry (64), address modification circuitry (66), and cacheability modification circuitry (68). If the burst ordering logic detects a cacheable requested address that will cause a cache line fill using an ascending burst order, that requested address is passed through to the bus interface unit for servicing as a normal cache line fill. If, however, the requested address would result in a descending burst order, the cacheability modification circuit modifies cacheability to cause the microprocessor to assert PCD (page cache disable), signaling to the system logic that the requested address is noncacheable--the system logic responds with a single non-burst transfer (1+) of the requested address. The request modification circuitry then signals a burst transfer request for a cache line fill, and the address modification circuitry modifies the requested address to provide a bus cycle address that is within the cache line that contains the requested address but will result in an ascending burst order to transfer that cache line (+4).

Abstract translation: 在示例性实施例中，使用突发排序逻辑来在486计算机系统中实现用于高速缓存行填充的仅上升的突发排序，同时保持与常规486突发排序的兼容性，该序列使用上升和下降突发命令，这取决于请求的位置 高速缓存行中的地址（临界Dword）（传统的486突发排序在后台的表1中示出）。 突发排序逻辑（60）对所请求的地址实施1 + 4突发排序，对于传统的486突发排序，将导致下降的突发顺序（示例性的1 + 4突发排序在说明书中的表2中示出）。 突发排序逻辑包括请求修改电路（64），地址修改电路（66）和高速缓存修改电路（68）。 如果突发排序逻辑检测到可缓存请求的地址，该地址将使用升序突发顺序引起高速缓存行填充，则该请求的地址被传递到总线接口单元，用于作为正常的高速缓存行填充进行服务。 然而，如果所请求的地址将导致下降的突发顺序，则高速缓存修改电路修改高速缓存以使微处理器断言PCD（页面缓存禁用），向系统逻辑指示所请求的地址不可写 - 系统逻辑响应 请求地址的单个非突发传输（1+）。 然后，请求修改电路发出用于高速缓存线填充的突发传送请求，并且地址修改电路修改所请求的地址以提供位于包含所请求的地址的高速缓存行内的总线周期地址，但将导致上升的突发顺序 传输该缓存行（+4）。