公开(公告)号：US5838897A

公开(公告)日：1998-11-17

申请号：US606774

申请日：1996-02-27

Applicant: Mark W. Bluhm ,  Mark W. Hervin

Inventor： Mark W. Bluhm ,  Mark W. Hervin

IPC: G06F11/267 ,  G06F11/36 ,  G06F11/00

CPC classification number: G06F11/2236 ,  G06F11/3656

Abstract: A processor for outputting processor state information during idle bus cycles to facilitate the diagnosing and debugging of a processor. The processor includes a plurality of external pins for communicating data from the processor; a visibility register for selecting one of a plurality of modes which identifies processor state information to output onto the plurality of external pins; and a bus interface unit for communicating data to the external pins of the processor and for detecting an idle bus cycle. The bus interface unit outputs processor state information according to the identified mode onto the plurality of external pins in response to detecting an idle bus cycle.

Abstract translation: 一种用于在空闲总线周期期间输出处理器状态信息以便于诊断和调试处理器的处理器。 处理器包括用于从处理器传送数据的多个外部引脚; 可见度寄存器，用于选择识别处理器状态信息以输出到所述多个外部引脚上的多个模式之一; 以及用于将数据传送到处理器的外部引脚并用于检测空闲总线周期的总线接口单元。 响应于检测到空闲总线周期，总线接口单元根据识别的模式向多个外部引脚输出处理器状态信息。

公开(公告)号：US5835949A

公开(公告)日：1998-11-10

申请号：US831842

申请日：1997-04-02

Applicant: Marc A. Quattromani ,  Raul A. Garibay, Jr. ,  Steven C. McMahan ,  Mark W. Hervin

Inventor： Marc A. Quattromani ,  Raul A. Garibay, Jr. ,  Steven C. McMahan ,  Mark W. Hervin

IPC: G06F9/38

CPC classification number: G06F9/3812

Abstract: A system and method of readily identifying and handling self-modifying variable length instructions in a pipelined processor is disclosed employing index tags associated with each stage of the execution pipeline wherein the index tags identify the cache line numbers in the instruction cache from which the instructions originate.

Abstract translation: 公开了一种在流水线处理器中容易地识别和处理自修改可变长度指令的系统和方法，其采用与执行流水线的每个级相关联的索引标签，其中索引标签识别指令来自的指令高速缓存中的高速缓存行数 。

公开(公告)号：US5805879A

公开(公告)日：1998-09-08

申请号：US604788

申请日：1996-02-23

Applicant: Mark W. Hervin ,  Raul A. Garibay, Jr.

Inventor： Mark W. Hervin ,  Raul A. Garibay, Jr.

IPC: G06F9/30 ,  G06F9/355 ,  G06F9/38 ,  G06F9/34

CPC classification number: G06F9/342 ,  G06F9/30101 ,  G06F9/30138 ,  G06F9/3861

Abstract: In a pipelined processor having at least one execution pipeline for executing instructions, the execution pipeline including ID (decode), AC (address calculation), and EX (execution) processing stages, the processor capable of addressing segments of system memory coupled thereto, a circuit for, and method of, setting a segment access indicator associated with a segment of the system memory being accessed by the processor. The circuit includes: (a) exception generating circuitry to generate an exception when the segment access indicator requires setting and (b) exception handling circuitry, invoked by the processor in response to generation of the exception, to flush the execution pipeline of instructions following a segment load instruction, set the segment access indicator and load an address pointer of the processor with an address corresponding to a specified location within the segment.

Abstract translation: 在具有用于执行指令的至少一个执行流水线的流水线处理器中，执行流水线包括ID（解码），AC（地址计算）和EX（执行）处理阶段，处理器能够寻址与其耦合的系统存储器的段， 电路和设置与由处理器访问的系统存储器的段相关联的段访问指示符的方法。 该电路包括：（a）异常产生电路，用于当段访问指示符需要设置时产生异常;以及（b）由处理器响应异常生成而调用的异常处理电路，以刷新指令之后的执行流水线 段加载指令，设置段访问指示符，并加载处理器的地址指针，该地址指针与段内指定位置相对应的地址。

公开(公告)号：US5794026A

公开(公告)日：1998-08-11

申请号：US138660

申请日：1993-10-18

Applicant: Mark W. Hervin ,  Ronald S. McMahon

Inventor： Mark W. Hervin ,  Ronald S. McMahon

IPC: G06F9/26 ,  G06F9/28 ,  G06F9/30

CPC classification number: G06F9/30145 ,  G06F9/265 ,  G06F9/28

Abstract: A processor architecture and methodology for executing a condition dependent instruction over a plurality of execution stages in a microprocessor. The microprocessor includes a memory for storing microinstructions. The method involves various steps. In one step, an instruction is received. In another step, a first microinstruction is issued from the memory. This first microinstruction comprises a control and a base address. In yet another step, a secondary address is determined, external from the memory, by evaluating a plurality of predetermined data. In a still another step, the base address and the secondary address are combined to form a destination address in response to the control signal, wherein the destination address identifies a second microinstruction in the memory to execute a successive stage for the received instruction.

Abstract translation: 一种用于在微处理器中的多个执行阶段执行与条件相关的指令的处理器架构和方法。 微处理器包括用于存储微指令的存储器。 该方法涉及各种步骤。 一步，接收指令。 在另一步骤中，从存储器发出第一微指令。 该第一微指令包括控制和基地址。 在另一步骤中，通过评估多个预定数据，从存储器外部确定辅助地址。 在另一步骤中，响应于控制信号将基地址和次地址组合成目的地地址，其中目的地地址识别存储器中的第二微指令以执行接收到的指令的连续级。

公开(公告)号：US5742755A

公开(公告)日：1998-04-21

申请号：US603999

申请日：1996-02-20

Applicant: Mark W. Hervin

Inventor： Mark W. Hervin

IPC: G06F11/07 ,  G06F11/00 ,  G06F12/00

CPC classification number: G06F11/0751 ,  G06F11/0721

Abstract: In an .chi.86-compatible processor capable of operating in a protected mode of operation in which privilege levels are assigned to tasks executing therein, an application task being assigned a lowest privilege level and executable in the processor to cause the processor to calculate addresses corresponding to specific locations in a computer memory associated with the processor, the addresses to be in alignment with respect to the computer memory prior to the processor issuing the addresses, a circuit for, and method of, handling sequential alignment faults and a computer system embodying the same. The circuit includes: (1) an alignment detection circuit to detect an alignment fault and generate an alignment check exception in response thereto and (2) an alignment fault-handling routine associated with the processor, executable in response to generation of the alignment check exception, operable to detect a sequential alignment fault and generate a double fault exception in response thereto, the alignment fault-handling routine thereby allowing the processor to avoid a third sequential alignment fault.

Abstract translation: 在能够在受保护的操作模式中操作的chi 86兼容处理器中，其中特权级别被分配给在其中执行的任务，应用任务被分配最低权限级别并且可在处理器中执行以使处理器计算对应于 与处理器相关联的计算机存储器中的特定位置，在处理器发布地址之前相对于计算机存储器对准的地址，处理顺序对准故障的电路和方法以及体现其的计算机系统 。 电路包括：（1）对准检测电路，用于检测对准故障并响应于此产生对准检查异常，以及（2）与处理器相关联的对准故障处理例程，可响应于对准检查异常 ，可操作以检测顺序对准故障并响应于此而产生双重故障异常，所述对准故障处理例程由此允许处理器避免第三次顺序对准故障。

公开(公告)号：US5644741A

公开(公告)日：1997-07-01

申请号：US138855

申请日：1993-10-18

Applicant: Mark W. Bluhm ,  Mark W. Hervin ,  Steven C. McMahan ,  Raul A. Garibay, Jr.

Inventor： Mark W. Bluhm ,  Mark W. Hervin ,  Steven C. McMahan ,  Raul A. Garibay, Jr.

IPC: G06F9/26 ,  G06F9/28 ,  G06F9/30 ,  G06F9/22

CPC classification number: G06F9/265 ,  G06F9/28 ,  G06F9/30145

Abstract: A processor includes storage circuitry for storing an instruction and memory circuitry addressable by a microaddress for outputting a microinstruction in response to the microaddress. The processor further includes sequencing circuitry coupled to provide the microaddress to the memory circuitry. Finally, the processor includes decode circuitry coupled to the storage circuitry for detecting whether the instruction stored in the storage circuitry comprises a single clock instruction before the memory circuit outputs the microinstruction, and for indicating to the sequencing circuitry in response to detecting whether the instruction stored in the storage circuitry comprises a single clock instruction.

Abstract translation: 处理器包括存储电路，用于存储可由微地址寻址的指令和存储器电路，用于响应于微地址输出微指令。 处理器还包括被连接以向存储器电路提供微地址的排序电路。 最后，处理器包括耦合到存储电路的解码电路，用于检测存储在存储电路中的指令是否在存储器电路输出微指令之前包括单个时钟指令，并且响应于检测指令是否存储 在存储电路中包括单个时钟指令。

公开(公告)号：US5596735A

公开(公告)日：1997-01-21

申请号：US606150

申请日：1996-02-23

Applicant: Mark W. Hervin ,  Raul A. Garibay, Jr.

Inventor： Mark W. Hervin ,  Raul A. Garibay, Jr.

IPC: G06F9/355 ,  G06F12/02 ,  G06F9/38 ,  G06F9/42

CPC classification number: G06F9/342 ,  G06F12/0292

Abstract: In a processor having a protected mode of operation in which a computer memory associated with the processor contains global and local descriptor tables addressed by a combination of a base address and an index, the processor having (i) global and local base address registers alternatively to provide the base address and (ii) a selector for containing the index and a table indicator (TI) bit indicating which of the global and local base address registers is to provide the base address, the processor requiring a time to derive the index and a value of the TI bit and a further time to combine the index and the base address, a base address register predicting circuit to predict, and a method of predicting, which of the global and local base address registers is to provide the base address without having to wait for the processor to derive the value of the TI bit. The circuit includes (i) TI bit predicting circuitry to generate a predicted value of the TI bit as a function of a prior value of the TI bit, and (ii) register access circuitry to access one of the global and local base address registers as a function of the predicted value of the TI bit.

Abstract translation: 在具有保护操作模式的处理器中，其中与处理器相关联的计算机存储器包含由基地址和索引的组合寻址的全局和本地描述符表，所述处理器具有（i）全局和本地基地址寄存器， 提供基地址和（ii）用于包含索引的选择器和指示全局和本地基地址寄存器中的哪一个提供基地址的表指示符（TI）位，处理器需要时间来导出索引，以及 TI比特的值以及组合索引和基地址的另外的时间，用于预测的基地址寄存器预测电路和预测全局和本地基地址寄存器中的哪一个将提供基地址而不具有 等待处理器导出TI位的值。 电路包括（i）TI比特预测电路，以产生作为TI比特的先前值的函数的TI比特的预测值，以及（ii）寄存器访问电路以访问全局和本地基地址寄存器之一作为 TI位的预测值的函数。

公开(公告)号：US6138230A

公开(公告)日：2000-10-24

申请号：US902908

申请日：1997-07-29

Applicant: Mark W. Hervin ,  Steven C. McMahan ,  Mark Bluhm ,  Raul A. Garibay, Jr.

Inventor： Mark W. Hervin ,  Steven C. McMahan ,  Mark Bluhm ,  Raul A. Garibay, Jr.

IPC: G06F9/38 ,  G06F9/00 ,  G06F11/30

CPC classification number: G06F9/3861 ,  G06F9/3838 ,  G06F9/3853 ,  G06F9/3867 ,  G06F9/3875

Abstract: A microprocessor comprises a plurality of instruction pipelines having a plurality of stages for processing a stream of instructions, circuitry for simultaneously issuing instructions into two or more of the pipelines without regard to whether one of the simultaneously issued instructions has a data dependency on other of the simultaneously issued instructions, detecting circuitry for detecting dependencies between instructions in the pipelines and circuitry for controlling the flow of instructions through the pipelines such that an instruction is not delayed due to a data dependency on another instruction unless the data dependency must be resolved for proper processing of the instruction in its current stage.

Abstract translation: 微处理器包括具有用于处理指令流的多个级的多条指令流水线，用于同时将指令发布到两条或更多条流水线中的电路，而不考虑同时发出的指令之一是否具有与其他 同时发出的指令，用于检测管道中的指令之间的依赖性的检测电路和用于控制通过管线的指令流的电路，使得由于对另一指令的数据依赖性而不指示指令，否则指令不被延迟，除非必须解决数据依赖性以进行适当的处​​理 的指示在当前阶段。

公开(公告)号：US5524222A

公开(公告)日：1996-06-04

申请号：US343277

申请日：1994-11-22

Applicant: Mark W. Hervin

Inventor： Mark W. Hervin

IPC: G06F9/26 ,  G06F9/32 ,  G06F15/00

CPC classification number: G06F9/30058 ,  G06F9/265

Abstract: A sequencer for use in a pipeline architecture includes circuitry for determining whether the previous instruction was a conditional jump instruction and whether the condition was met, circuitry for determining whether the current instruction is a conditional jump, and circuitry inhibiting a branch responsive to the current instruction, if the previous instruction was a conditional jump and the condition was met. Additionally, circuitry may be provided for treating a CALL instruction as a one-cycle unconditional jump if the preceding instruction was a conditional jump and the condition was not met, thereby implementing a two-cycle IF-THEN-ELSE instruction.

Abstract translation: 用于流水线架构的定序器包括用于确定先前指令是否为条件跳转指令以及该条件是否满足的电路，用于确定当前指令是否为条件跳转的电路，以及响应于当前指令禁止分支的电路 如果先前的指令是条件跳转，并且满足条件。 另外，如果先前的指令是条件跳转并且条件不满足，则可以提供用于将CALL指令作为单周期无条件跳转来处理的电路，从而实现两周期IF-THEN-ELSE指令。

公开(公告)号：US06205560B1

公开(公告)日：2001-03-20

申请号：US08606769

申请日：1996-02-27

Applicant: Mark W. Hervin ,  Mark W. Bluhm ,  Stanley D. Harder ,  William C. Patton

Inventor： Mark W. Hervin ,  Mark W. Bluhm ,  Stanley D. Harder ,  William C. Patton

IPC: H02H305

CPC classification number: G06F11/2236 ,  G06F11/3656

Abstract: A circuit for diagnosing and debugging a processor for executing a stream of instructions that includes a set of debug registers for identifying an instruction or data address breakpoint; a processor for generating a debug exception in response to an instruction or data address in the stream of instructions matching the instruction or data breakpoint stored in the set of debug registers and a debug configuration register for enabling transfer of program control to one of a plurality of destinations in response to the debug exception. The debug configuration registers may designate system management mode, JTAG routine or a software debug interrupt handler as the destination.

Abstract translation: 一种用于诊断和调试处理器的电路，用于执行包括用于识别指令或数据地址断点的一组调试寄存器的指令流; 用于响应于与存储在所述一组调试寄存器中的指令或数据断点相匹配的指令流中的指令或数据地址产生调试异常的处理器和用于使程序控制能够传送到多个 响应调试异常的目的地。 调试配置寄存器可以指定系统管理模式，JTAG程序或软件调试中断处理程序作为目标。