公开(公告)号：US20220005733A1

公开(公告)日：2022-01-06

申请号：US17231214

申请日：2021-04-15

申请人： MagnaChip Semiconductor, Ltd.

发明人： Jin Won JEONG ,  Jang Hee LEE ,  Young Hun JUN ,  Jong Woon LEE ,  Jae Sik CHOI

IPC分类号： H01L21/78 ,  H01L21/66 ,  H01L23/31 ,  H01L21/56 ,  H01L23/10

摘要： A method for forming a semiconductor die, includes forming an interlayer dielectric layer on a substrate having a semiconductor die region, a seal-ring region, and a scribe line region, forming a metal pad and a test pad on the interlayer dielectric layer, forming a passivation dielectric layer on the interlayer dielectric layer, the metal pad, and the test pad, first etching the passivation dielectric layer and the interlayer dielectric layer existing between the seal-ring region and the scribe line region to a predetermined depth using a plasma etching process, second etching the passivation dielectric layer to expose the metal pad and the test pad, forming a bump on the metal pad, and dicing the substrate while removing the scribe line region by mechanical sawing.

公开(公告)号：US20210407854A1

公开(公告)日：2021-12-30

申请号：US17231074

申请日：2021-04-15

申请人： MagnaChip Semiconductor, Ltd.

发明人： Jin Won JEONG ,  Jae Sik CHOI ,  Byeung Soo SONG

IPC分类号： H01L21/78 ,  H01L21/304 ,  H01L21/67 ,  H01L21/268

摘要： A semiconductor die forming method includes preparing a wafer, forming a low-k dielectric layer on the wafer, forming a metal pad on the low-k dielectric layer, forming a passivation layer on the metal pad, patterning the passivation layer, laser grooving the low-k dielectric layer using an ultrashort pulse laser, and cutting the wafer by mechanical sawing to form one or more semiconductor dies.

公开(公告)号：US20190079114A1

公开(公告)日：2019-03-14

申请号：US15992543

申请日：2018-05-30

申请人： MagnaChip Semiconductor, Ltd.

发明人： Jae Sik CHOI ,  Jin Won JEONG ,  Young Sug SEONG ,  Dong Keun LEE

IPC分类号： G01R1/04

摘要： A test socket of a flexible semiconductor chip package includes a first bending jig having a convex contour, a second bending jig having a concave contour, and a semiconductor chip package. The second bending jig is disposed to matingly engage the first bending jig. The semiconductor chip package is disposed between the first bending jig and the second bending jig, and includes a flexible tape and a semiconductor chip. The semiconductor chip is disposed on a surface of the flexible tape. Each of the first and second bending jigs has a horizontal length longer than a length of the semiconductor chip and less than a length of the flexible tape.

公开(公告)号：US20240128123A1

公开(公告)日：2024-04-18

申请号：US18542991

申请日：2023-12-18

申请人： MagnaChip Semiconductor, Ltd.

发明人： Jin Won JEONG ,  Jang Hee LEE ,  Young Hun JUN ,  Jong Woon LEE ,  Jae Sik CHOI

IPC分类号： H01L21/78 ,  H01L21/56 ,  H01L21/66 ,  H01L23/10 ,  H01L23/31

CPC分类号： H01L21/78 ,  H01L21/56 ,  H01L22/14 ,  H01L22/32 ,  H01L23/10 ,  H01L23/3171

摘要： A method for forming a semiconductor die, includes forming an interlayer dielectric layer on a substrate having a semiconductor die region, a seal-ring region, and a scribe line region, forming a metal pad and a test pad on the interlayer dielectric layer, forming a passivation dielectric layer on the interlayer dielectric layer, the metal pad, and the test pad, first etching the passivation dielectric layer and the interlayer dielectric layer existing between the seal-ring region and the scribe line region to a predetermined depth using a plasma etching process, second etching the passivation dielectric layer to expose the metal pad and the test pad, forming a bump on the metal pad, and dicing the substrate while removing the scribe line region by mechanical sawing.

公开(公告)号：US20210296271A1

公开(公告)日：2021-09-23

申请号：US16934338

申请日：2020-07-21

申请人： MagnaChip Semiconductor, Ltd.

发明人： Jin Won JEONG ,  Jae Sik CHOI ,  Byeung Soo SONG

IPC分类号： H01L23/00 ,  H01L21/78 ,  H01L21/3065 ,  H01L21/268 ,  H01L21/304 ,  H01L51/00 ,  H01L51/56 ,  H01L25/16

摘要： A semiconductor chip packaging method includes forming a bump on a wafer, forming a coating film covering the bump, laser grooving the wafer, plasma etching the wafer on which the laser grooving is performed, exposing the bump by removing the coating film covering the bump, fabricating a semiconductor die by performing mechanical sawing of the wafer, and packaging the semiconductor die.

公开(公告)号：US20180358285A1

公开(公告)日：2018-12-13

申请号：US15859988

申请日：2018-01-02

申请人： MagnaChip Semiconductor, Ltd.

发明人： Si Hyeon GO ,  Jae Sik CHOI ,  Myung Ho PARK ,  Dong Seong OH ,  Beom Su KIM

IPC分类号： H01L23/495 ,  H01L29/417 ,  H01L29/423 ,  H01L25/07 ,  H01L25/18

CPC分类号： H01L23/4951 ,  H01L23/49562 ,  H01L23/49575 ,  H01L25/07 ,  H01L25/18 ,  H01L29/41775 ,  H01L29/42356 ,  H01L2224/16245

摘要： A multi-chip package of power semiconductor includes a lead frame, a first segment group, a second segment group, a first power semiconductor chip and a second power semiconductor chip. The lead frame includes a first segment group having a first gate segment, a first source segment, and a first drain segment that are separated from each other. The second segment group has a second gate segment, a second source segment, and a second drain segment that are separated from each other. The first power semiconductor chip is formed on the first segment group. The second power semiconductor chip is formed on the second segment group. The first source segment is physically connected to the second drain segment.

公开(公告)号：US20170287821A1

公开(公告)日：2017-10-05

申请号：US15244846

申请日：2016-08-23

申请人： Magnachip Semiconductor, Ltd.

发明人： Jae Sik CHOI ,  Si Hyeon GO ,  Jun Young HEO ,  Moon Taek SUNG ,  Dong Seong OH

IPC分类号： H01L23/495 ,  H01L21/48 ,  H01L23/373 ,  H01L25/18 ,  H01L23/00

CPC分类号： H01L23/49575 ,  H01L21/4875 ,  H01L23/3735 ,  H01L23/49531 ,  H01L23/49537 ,  H01L23/49541 ,  H01L23/49562 ,  H01L24/14 ,  H01L24/48 ,  H01L24/85 ,  H01L25/18 ,  H01L2224/05552 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/48247 ,  H01L2924/00014 ,  H01L2924/1203 ,  H01L2924/13055 ,  H01L2224/45099

摘要： A power semiconductor module includes: a substrate including first, second, and third metal patterns separated from each other, a semiconductor element located on the substrate, a lead frame located on the substrate and including first, second, third, and fourth bodies; a first terminal connected to the first body, a second terminal connected to the second body, and a third common terminal that connects the third body and the fourth body, wherein a length of the third common terminal is longer than that of the first and second terminals.

公开(公告)号：US20220278064A1

公开(公告)日：2022-09-01

申请号：US17747124

申请日：2022-05-18

申请人： MagnaChip Semiconductor, Ltd.

发明人： Jin Won JEONG ,  Jae Sik CHOI ,  Byeung Soo SONG

IPC分类号： H01L23/00 ,  H01L21/3065 ,  H01L21/268 ,  H01L21/304 ,  H01L51/00 ,  H01L51/56 ,  H01L25/16 ,  H01L21/78

摘要： A semiconductor chip packaging method includes forming a bump on a wafer, forming a coating film covering the bump, laser grooving the wafer, plasma etching the wafer on which the laser grooving is performed, exposing the bump by removing the coating film covering the bump, fabricating a semiconductor die by performing mechanical sawing of the wafer, and packaging the semiconductor die.

公开(公告)号：US20200286817A1

公开(公告)日：2020-09-10

申请号：US16503897

申请日：2019-07-05

申请人： MagnaChip Semiconductor, Ltd.

发明人： Jae Sik CHOI ,  Do Young KIM ,  Jin Won JEONG ,  Hye Ji LEE

IPC分类号： H01L23/498 ,  H01L27/12 ,  H01L23/528

摘要： A semiconductor package includes a first metal interconnection disposed in a semiconductor chip, a first bump group configured to be connected to the first metal interconnection, a first inner lead pattern group configured to be connected to the first bump group, a second metal interconnection disposed in the semiconductor chip, a second bump group configured to be connected to the second metal interconnection; and a second inner lead pattern group configured to be connected to the second bump group, wherein a density of the first metal interconnection is greater than a density of the second metal interconnection, such that a first pitch of the first lead pattern group is greater than a second pitch of the second lead pattern group.

公开(公告)号：US20200035644A1

公开(公告)日：2020-01-30

申请号：US16392388

申请日：2019-04-23

申请人： Magnachip Semiconductor, Ltd.

发明人： Jae Sik CHOI ,  Jin Won JEONG ,  Do Young KIM ,  Hye Ji LEE ,  Byeung Soo SONG

IPC分类号： H01L23/00 ,  H01L23/498 ,  H01L23/60

摘要： A semiconductor package manufacturing method includes preparing a flexible film including input wire patterns and output wire patterns, preparing a semiconductor chip including metal bumps, attaching the semiconductor chip to one side of the flexible film, such that the metal bumps are connected to either one or both of the input wire patterns and the output wire patterns, and attaching a first absorbing and shielding tape to another side of the flexible film, wherein the first absorbing and shielding tape includes an absorption film and a protective insulating film disposed on the absorption film.