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公开(公告)号：US20190198415A1
公开(公告)日：2019-06-27
申请号：US16293936
申请日：2019-03-06
发明人： Jae Sik CHOI , Dong Seong OH , Si Hyeon GO
IPC分类号： H01L23/367 , H01L23/00 , H01L23/544 , H01L21/56 , H01L21/48 , H01L23/485
CPC分类号： H01L23/367 , H01L21/4853 , H01L21/56 , H01L21/561 , H01L21/568 , H01L23/3107 , H01L23/4334 , H01L23/485 , H01L23/544 , H01L24/83 , H01L2223/54433 , H01L2223/5448 , H01L2223/54486
摘要： A method to manufacture a semiconductor package includes: preparing a metal substrate; attaching semiconductor dies to the metal substrate at an interval; attaching a bonding film to the semiconductor dies; applying a mold material on the semiconductor dies and the metal substrate, and curing the mold material to form a mold member; grinding the mold member and the metal substrate to a thickness; removing the bonding film; attaching a redistribution layer to the semiconductor dies; and cutting between the semiconductor dies.
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公开(公告)号：US20180151465A1
公开(公告)日：2018-05-31
申请号：US15491025
申请日：2017-04-19
发明人： Jae Sik CHOI , Dong Seong OH , Si Hyeon GO
IPC分类号： H01L23/367 , H01L23/485 , H01L23/544 , H01L21/48 , H01L21/56
CPC分类号： H01L23/367 , H01L21/4853 , H01L21/561 , H01L23/485 , H01L23/544 , H01L2223/5448
摘要： A method to manufacture a semiconductor package includes: preparing a metal substrate; attaching semiconductor dies to the metal substrate at an interval; attaching a bonding film to the semiconductor dies; applying a mold material on the semiconductor dies and the metal substrate, and curing the mold material to form a mold member; grinding the mold member and the metal substrate to a thickness; removing the bonding film; attaching a redistribution layer to the semiconductor dies; and cutting between the semiconductor dies.
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公开(公告)号：US20180358285A1
公开(公告)日：2018-12-13
申请号：US15859988
申请日：2018-01-02
发明人： Si Hyeon GO , Jae Sik CHOI , Myung Ho PARK , Dong Seong OH , Beom Su KIM
IPC分类号： H01L23/495 , H01L29/417 , H01L29/423 , H01L25/07 , H01L25/18
CPC分类号： H01L23/4951 , H01L23/49562 , H01L23/49575 , H01L25/07 , H01L25/18 , H01L29/41775 , H01L29/42356 , H01L2224/16245
摘要： A multi-chip package of power semiconductor includes a lead frame, a first segment group, a second segment group, a first power semiconductor chip and a second power semiconductor chip. The lead frame includes a first segment group having a first gate segment, a first source segment, and a first drain segment that are separated from each other. The second segment group has a second gate segment, a second source segment, and a second drain segment that are separated from each other. The first power semiconductor chip is formed on the first segment group. The second power semiconductor chip is formed on the second segment group. The first source segment is physically connected to the second drain segment.
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公开(公告)号：US20170287821A1
公开(公告)日：2017-10-05
申请号：US15244846
申请日：2016-08-23
发明人： Jae Sik CHOI , Si Hyeon GO , Jun Young HEO , Moon Taek SUNG , Dong Seong OH
IPC分类号： H01L23/495 , H01L21/48 , H01L23/373 , H01L25/18 , H01L23/00
CPC分类号： H01L23/49575 , H01L21/4875 , H01L23/3735 , H01L23/49531 , H01L23/49537 , H01L23/49541 , H01L23/49562 , H01L24/14 , H01L24/48 , H01L24/85 , H01L25/18 , H01L2224/05552 , H01L2224/05554 , H01L2224/0603 , H01L2224/48247 , H01L2924/00014 , H01L2924/1203 , H01L2924/13055 , H01L2224/45099
摘要： A power semiconductor module includes: a substrate including first, second, and third metal patterns separated from each other, a semiconductor element located on the substrate, a lead frame located on the substrate and including first, second, third, and fourth bodies; a first terminal connected to the first body, a second terminal connected to the second body, and a third common terminal that connects the third body and the fourth body, wherein a length of the third common terminal is longer than that of the first and second terminals.
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