知搜-全球专利检索

  1. 登录
  2. 注册

搜索结果

60 条记录 (耗时 0.025 秒)

    BIPOLAR JUNCTION TRANSISTOR STRUCTURE FOR REDUCED CURRENT CROWDING
    1.
    发明申请
    BIPOLAR JUNCTION TRANSISTOR STRUCTURE FOR REDUCED CURRENT CROWDING 有权
    用于减少电流冲击的双极接头晶体管结构

    公开(公告)号：US20130146894A1

    公开(公告)日：2013-06-13

    申请号：US13323297

    申请日：2011-12-12

    申请人： Lin Cheng ,  Anant K. Agarwal ,  Sei-Hyung Ryu

    发明人： Lin Cheng ,  Anant K. Agarwal ,  Sei-Hyung Ryu

    IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L29/24

    CPC分类号： H01L29/0688 ,  H01L29/1004 ,  H01L29/1602 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/66068 ,  H01L29/66272 ,  H01L29/732

    摘要： The present disclosure relates to a bipolar junction transistor (BJT) structure that significantly reduces current crowding while improving the current gain relative to conventional BJTs. The BJT includes a collector, a base region, and an emitter. The base region is formed over the collector and includes at least one extrinsic base region and an intrinsic base region that extends above the at least one extrinsic base region to provide a mesa. The emitter is formed over the mesa. The BJT may be formed from various material systems, such as the silicon carbide (SiC) material system. In one embodiment, the emitter is formed over the mesa such that essentially none of the emitter is formed over the extrinsic base regions. Typically, but not necessarily, the intrinsic base region is directly laterally adjacent the at least one extrinsic base region.

    摘要翻译： 本公开涉及一种双极结型晶体管（BJT）结构，其显着地减少了电流拥挤，同时改善了相对于传统BJT的电流增益。 BJT包括集电极，基极区和发射极。 基极区形成在集电极上，并且包括至少一个非本征基极区域和在至少一个外部基极区域上方延伸以提供台面的本征基极区域。 发射极形成在台面上。 BJT可以由诸如碳化硅（SiC）材料体系的各种材料体系形成。 在一个实施例中，发射极形成在台面之上，使得基本上在外部基极区域上不形成发射极。 通常但不一定，本征基区直接横向邻近于至少一个外在基区。

    SEMICONDUCTOR DEVICE HAVING HIGH PERFORMANCE CHANNEL
    3.
    发明申请
    SEMICONDUCTOR DEVICE HAVING HIGH PERFORMANCE CHANNEL 有权
    具有高性能通道的半导体器件

    公开(公告)号：US20120223330A1

    公开(公告)日：2012-09-06

    申请号：US13039441

    申请日：2011-03-03

    申请人： Sarit Dhar ,  Sei-Hyung Ryu ,  Lin Cheng ,  Anant Agarwal

    发明人： Sarit Dhar ,  Sei-Hyung Ryu ,  Lin Cheng ,  Anant Agarwal

    IPC分类号： H01L29/161 ,  H01L21/22

    CPC分类号： H01L29/107 ,  H01L21/225 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/66477 ,  H01L29/66568

    摘要： Semiconductor devices having a high performance channel and method of fabrication thereof are disclosed. Preferably, the semiconductor devices are Metal-Oxide-Semiconductor (MOS) devices, and even more preferably the semiconductor devices are Silicon Carbide (SiC) MOS devices. In one embodiment, a semiconductor device includes a SiC substrate of a first conductivity type, a first well of a second conductivity type, a second well of the second conductivity type, and a surface diffused channel of the second conductivity type formed at the surface of semiconductor device between the first and second wells. A depth and doping concentration of the surface diffused channel are controlled to provide increased carrier mobility for the semiconductor device as compared to the same semiconductor device without the surface diffused channel region when in the on-state while retaining a turn-on, or threshold, voltage that provides normally-off behavior.

    摘要翻译： 公开了具有高性能通道的半导体器件及其制造方法。 优选地，半导体器件是金属氧化物半导体（MOS）器件，并且甚至更优选半导体器件是碳化硅（SiC）MOS器件。 在一个实施例中，半导体器件包括第一导电类型的SiC衬底，第二导电类型的第一阱，第二导电类型的第二阱以及形成在第二导电类型的表面处的第二导电类型的表面扩散沟道 半导体器件在第一和第二阱之间。 控制表面扩散通道的深度和掺杂浓度，以便在处于导通状态同时保持导通状态或阈值时，与没有表面扩散沟道区的相同半导体器件相比，为半导体器件提供增加的载流子迁移率， 电压提供常态动作。

    Semiconductor device having high performance channel
    4.
    发明授权
    Semiconductor device having high performance channel 有权
    具有高性能通道的半导体器件

    公开(公告)号：US09478616B2

    公开(公告)日：2016-10-25

    申请号：US13039441

    申请日：2011-03-03

    申请人： Sarit Dhar ,  Sei-Hyung Ryu ,  Lin Cheng ,  Anant Agarwal

    发明人： Sarit Dhar ,  Sei-Hyung Ryu ,  Lin Cheng ,  Anant Agarwal

    IPC分类号： H01L29/15 ,  H01L31/0312 ,  H01L29/10 ,  H01L21/225 ,  H01L29/16 ,  H01L29/66

    CPC分类号： H01L29/107 ,  H01L21/225 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/66477 ,  H01L29/66568

    摘要： Semiconductor devices having a high performance channel and method of fabrication thereof are disclosed. Preferably, the semiconductor devices are Metal-Oxide-Semiconductor (MOS) devices, and even more preferably the semiconductor devices are Silicon Carbide (SiC) MOS devices. In one embodiment, a semiconductor device includes a SiC substrate of a first conductivity type, a first well of a second conductivity type, a second well of the second conductivity type, and a surface diffused channel of the second conductivity type formed at the surface of semiconductor device between the first and second wells. A depth and doping concentration of the surface diffused channel are controlled to provide increased carrier mobility for the semiconductor device as compared to the same semiconductor device without the surface diffused channel region when in the on-state while retaining a turn-on, or threshold, voltage that provides normally-off behavior.

    摘要翻译： 公开了具有高性能通道的半导体器件及其制造方法。 优选地，半导体器件是金属氧化物半导体（MOS）器件，并且甚至更优选半导体器件是碳化硅（SiC）MOS器件。 在一个实施例中，半导体器件包括第一导电类型的SiC衬底，第二导电类型的第一阱，第二导电类型的第二阱以及形成在第二导电类型的表面处的第二导电类型的表面扩散沟道 半导体器件在第一和第二阱之间。 控制表面扩散通道的深度和掺杂浓度，以便在处于导通状态同时保持导通状态或阈值时，与没有表面扩散沟道区的相同半导体器件相比，为半导体器件提供增加的载流子迁移率， 电压提供常态动作。

    Field effect transistor devices with low source resistance
    5.
    发明授权
    Field effect transistor devices with low source resistance 有权
    具有低源电阻的场效应晶体管器件

    公开(公告)号：US09029945B2

    公开(公告)日：2015-05-12

    申请号：US13102510

    申请日：2011-05-06

    申请人： Sei-Hyung Ryu ,  Doyle Craig Capell ,  Lin Cheng ,  Sarit Dhar ,  Charlotte Jonas ,  Anant Agarwal ,  John Palmour

    发明人： Sei-Hyung Ryu ,  Doyle Craig Capell ,  Lin Cheng ,  Sarit Dhar ,  Charlotte Jonas ,  Anant Agarwal ,  John Palmour

    IPC分类号： H01L29/66 ,  H01L29/15 ,  H01L31/0312 ,  H01L29/78 ,  H01L29/06 ,  H01L29/739 ,  H01L29/04 ,  H01L29/16

    CPC分类号： H01L29/7802 ,  H01L29/045 ,  H01L29/0696 ,  H01L29/1608 ,  H01L29/7395

    摘要： A semiconductor device includes a drift layer having a first conductivity type, a well region in the drift layer having a second conductivity type opposite the first conductivity type, and a source region in the well region. The source region has the first conductivity type and defines a channel region in the well region. The source region includes a lateral source region adjacent the channel region and a plurality of source contact regions extending away from the lateral source region opposite the channel region. A body contact region having the second conductivity type is between at least two of the plurality of source contact regions and is in contact with the well region. A source ohmic contact overlaps at least one of the source contact regions and the body contact region. A minimum dimension of a source contact area of the semiconductor device is defined by an area of overlap between the source ohmic contact and the at least one source contact region.

    摘要翻译： 半导体器件包括具有第一导电类型的漂移层，漂移层中具有与第一导电类型相反的第二导电类型的阱区，以及阱区中的源极区。 源区具有第一导电类型并且在阱区中限定沟道区。 源极区域包括与沟道区域相邻的横向源极区域和远离与沟道区域相对的横向源极区域延伸的多个源极接触区域。 具有第二导电类型的体接触区域在多个源极接触区域中的至少两个之间并且与阱区域接触。 源欧姆触点与源极接触区域和身体接触区域中的至少一个重叠。 半导体器件的源极接触区域的最小尺寸由源极欧姆接触和至少一个源极接触区域之间的重叠区域限定。

    Field effect transistor devices with low source resistance
    10.
    发明授权
    Field effect transistor devices with low source resistance 有权
    具有低源电阻的场效应晶体管器件

    公开(公告)号：US09142662B2

    公开(公告)日：2015-09-22

    申请号：US13108440

    申请日：2011-05-16

    申请人： Sei-Hyung Ryu ,  Doyle Craig Capell ,  Lin Cheng ,  Sarit Dhar ,  Charlotte Jonas ,  Anant Agarwal ,  John Palmour

    发明人： Sei-Hyung Ryu ,  Doyle Craig Capell ,  Lin Cheng ,  Sarit Dhar ,  Charlotte Jonas ,  Anant Agarwal ,  John Palmour

    IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L29/739 ,  H01L29/04 ,  H01L29/16

    CPC分类号： H01L29/7802 ,  H01L29/045 ,  H01L29/0696 ,  H01L29/1608 ,  H01L29/7395

    摘要： A semiconductor device includes a drift layer having a first conductivity type, a well region in the drift layer having a second conductivity type opposite the first conductivity type, and a source region in the well region, The source region has the first conductivity type and defines a channel region in the well region. The source region includes a lateral source region adjacent the channel region and a plurality of source contact regions extending away from the lateral source region opposite the channel region. A body contact region having the second conductivity type is between at least two of the plurality of source contact regions and is in contact with the well region. A source ohmic contact overlaps at least one of the source contact regions and the body contact region. A minimum dimension of a source contact area of the semiconductor device is defined by an area of overlap between the source ohmic contact and the at least one source contact region.

    摘要翻译： 半导体器件包括具有第一导电类型的漂移层，漂移层中具有与第一导电类型相反的第二导电类型的阱区以及阱区中的源极区。源极区具有第一导电类型并且限定 在井区域中的通道区域。 源极区域包括与沟道区域相邻的横向源极区域和远离与沟道区域相对的横向源极区域延伸的多个源极接触区域。 具有第二导电类型的体接触区域在多个源极接触区域中的至少两个之间并且与阱区域接触。 源欧姆触点与源极接触区域和身体接触区域中的至少一个重叠。 半导体器件的源极接触区域的最小尺寸由源极欧姆接触和至少一个源极接触区域之间的重叠区域限定。