公开(公告)号：US20100123445A1

公开(公告)日：2010-05-20

申请号：US12487596

申请日：2009-06-18

申请人： Kwi Dong KIM ,  Jong Kee Kwon ,  Jong Dae Kim ,  Yong Seo Koo

发明人： Kwi Dong KIM ,  Jong Kee Kwon ,  Jong Dae Kim ,  Yong Seo Koo

IPC分类号： G05F1/618

CPC分类号： H02M1/08 ,  H02M2001/0032 ,  Y02B70/16

摘要： Provided are a switching circuit and a small-size high-efficiency direct current-to-direct current (DC-DC) converter for portable devices including the same. Using dynamic threshold-complementary metal oxide semiconductor (DT-CMOS) transistors having dynamic threshold voltages as a switching device, the switching circuit maintains a low threshold voltage in a normal mode to improve current drivability while reducing conduction loss, and maintains a high threshold voltage in a standby mode to minimize power consumption. When the switching circuit is employed in a DC-DC converter, power conversion efficiency can be improved by reducing conduction loss in the normal mode, and power consumption can be minimized in the standby mode. Consequently, the DC-DC converter can maximize a use time of a battery of a portable device and can be useful in power supplies of portable devices that are gradually being miniaturized.

摘要翻译： 提供了一种用于包括其的便携式设备的开关电路和小尺寸高效率直流 - 直流（DC-DC）转换器。 使用具有动态阈值电压的动态阈值互补金属氧化物半导体（DT-CMOS）晶体管作为开关器件，开关电路在正常模式下维持低阈值电压，从而改善电流驱动能力，同时降低导通损耗，并保持高阈值电压 处于待机模式以最小化功耗。 当在DC-DC转换器中采用开关电路时，可以通过降低正常模式下的导通损耗来提高功率转换效率，并且在待机模式下功耗可以最小化。 因此，DC-DC转换器可以使便携式设备的电池的使用时间最大化，并且可以用于逐渐小型化的便携式设备的电源。

公开(公告)号：US20090033530A1

公开(公告)日：2009-02-05

申请号：US12027495

申请日：2008-02-07

申请人： Young Deuk JEON ,  Young Kyun CHO ,  Kwi Dong KIM ,  Jong Kee KWON ,  Jong Dae KIM ,  Seung Chul LEE

发明人： Young Deuk JEON ,  Young Kyun CHO ,  Kwi Dong KIM ,  Jong Kee KWON ,  Jong Dae KIM ,  Seung Chul LEE

IPC分类号： H03M1/00

CPC分类号： H03M1/1245 ,  H03M1/002 ,  H03M1/44

摘要： Provided are a pipeline Analog-to-Digital Converter (ADC) without a front-end Sample-and-Hold Amplifier (SHA) and a method of controlling the same. The method includes the steps of: simultaneously sampling, at an ADC and a residual signal generator included in a first stage, an analog input signal and respectively generating a first sampling value and a second sampling value; holding, at the residual signal generator, the second sampling value, and simultaneously amplifying and converting, at the ADC, the first sampling value into a corresponding digital code; and generating, at the residual signal generator, a residual signal using the digital code. The pipeline ADC and method of controlling the same minimize sampling mismatch caused by removing a front-end SHA, thereby ensuring stable performance without a front-end SHA. Since a front-end SHA is not used, it is possible to reduce chip size and power consumption, and improve the performance of the ADC.

摘要翻译： 提供了没有前端采样保持放大器（SHA）的管线模数转换器（ADC）及其控制方法。 该方法包括以下步骤：在ADC和包括在第一级中的残余信号发生器同时对模拟输入信号进行采样，并分别产生第一采样值和第二采样值; 在剩余信号发生器处保持​​第二采样值，并且同时在ADC处放大并转换第一采样值为相应的数字代码; 以及在剩余信号发生器处产生使用数字码的残留信号。 流水线ADC和控制相同的方法最小化了通过去除前端SHA引起的采样失配，从而确保了没有前端SHA的稳定性能。 由于不使用前端SHA，因此可以减少芯片尺寸和功耗，并提高ADC的性能。

公开(公告)号：US20080136699A1

公开(公告)日：2008-06-12

申请号：US11946583

申请日：2007-11-28

申请人： Seung Chul LEE ,  Young Deuk JEON ,  Kwi Dong KIM ,  Jong Kee KWON

发明人： Seung Chul LEE ,  Young Deuk JEON ,  Kwi Dong KIM ,  Jong Kee KWON

IPC分类号： H03M1/38

CPC分类号： H03M1/0678 ,  H03M1/162

摘要： Provided is an algorithm analog-to-digital converter (ADC). The algorithm ADC obtains two digital outputs through different capacitor connections for one analog input signal and adds the digital output signals to obtain a final output value, so that a mismatch factor of the capacitor is removed to minimize a linearity limitation resulting from the capacitor mismatch. In addition, the algorithm ADC minimizes power consumption by making the operating frequency slow at a cycle requiring a high resolution and making the operating frequency fast at a cycle requiring a low resolution, i.e., outputting different operating clock frequencies according to a required resolution.

摘要翻译： 提供了一种算法模数转换器（ADC）。 算法ADC通过不同的电容器连接获得两个数字输出，用于一个模拟输入信号，并将数字输出信号相加以获得最终输出值，从而消除电容器的失配因子，以最小化由电容器失配引起的线性限制。 此外，算法ADC通过使工作频率在需要高分辨率的周期中变慢，并使工作频率在需要低分辨率的周期（即，根据所需分辨率输出不同的工作时钟频率）的情况下将功率消耗最小化。

公开(公告)号：US20120056654A1

公开(公告)日：2012-03-08

申请号：US12976449

申请日：2010-12-22

申请人： HUI DONG LEE ,  Seok Ju YUN ,  Kwi Dong KIM ,  Jong-Kee KWON ,  Sang-Hyun CHO

发明人： HUI DONG LEE ,  Seok Ju YUN ,  Kwi Dong KIM ,  Jong-Kee KWON ,  Sang-Hyun CHO

IPC分类号： H03L7/06

CPC分类号： H03L7/083 ,  H03J2200/10 ,  H03L7/0891 ,  H03L7/0995 ,  H03L7/187

摘要： Provided is a PLL circuit including automatic frequency control circuit and an operating method thereof. The voltage controlled oscillator is primarily controlled by an automatic frequency control circuit, and is secondarily controlled by a loop filter. The voltage controlled oscillator outputs a coarsely-tuned oscillation signal when primarily controlled, and outputs a finely-tuned oscillation signal when secondarily controlled. The PLL circuit can have a quick frequency fixing time, and output the oscillation signal having a broad and stable frequency. Moreover, the noise characteristic of the PLL circuit is enhanced.

摘要翻译： 提供一种包括自动频率控制电路的PLL电路及其操作方法。 压控振荡器主要由自动频率控制电路控制，二次由环路滤波器控制。 压控振荡器在主要受控时输出粗调谐振荡信号，并在二次控制时输出微调振荡信号。 PLL电路可以具有快速的频率固定时间，并输出具有宽而稳定频率的振荡信号。 此外，提高了PLL电路的噪声特性。

公开(公告)号：US20080136693A1

公开(公告)日：2008-06-12

申请号：US11950481

申请日：2007-12-05

申请人： Yi Gyeong KIM ,  Kwi Dong KIM ,  Chong Ki KWON ,  Jong Dae KIM

发明人： Yi Gyeong KIM ,  Kwi Dong KIM ,  Chong Ki KWON ,  Jong Dae KIM

IPC分类号： H03M3/00

CPC分类号： H03M3/374 ,  H03M3/338 ,  H03M3/424 ,  H03M3/45 ,  H03M3/452 ,  H03M3/454

摘要： Provided is a delta-sigma modulator including: a first integrator for integrating an input signal; an analog-to-digital converter for converting the integrated signal into a digital signal; and delay circuit for delaying an output signal of the analog-to-digital converter; and a differential delay circuit for differentially delaying the output signal of the analog-to-digital converter.

摘要翻译： 提供一种Δ-Σ调制器，包括：用于对输入信号进行积分的第一积分器; 用于将积分信号转换为数字信号的模拟 - 数字转换器; 以及用于延迟模数转换器的输出信号的延迟电路; 以及用于差分地延迟模数转换器的输出信号的差分延迟电路。

公开(公告)号：US20080136464A1

公开(公告)日：2008-06-12

申请号：US11933025

申请日：2007-10-31

申请人： Kwi Dong KIM ,  Chong Ki Kwon ,  Jong Dae Kim

发明人： Kwi Dong KIM ,  Chong Ki Kwon ,  Jong Dae Kim

IPC分类号： H03K3/00 ,  H01L21/8249

CPC分类号： H01L21/8249 ,  H01L27/0623 ,  H01L29/41708 ,  H01L29/7322 ,  H03F3/45085 ,  H03F3/45179 ,  H03F3/45502 ,  H03F2203/45008 ,  H03F2203/45082 ,  H03F2203/45418 ,  H03F2203/45424 ,  H03K5/003 ,  H03K19/01 ,  H04L25/0276 ,  H04L25/0282

摘要： Provided is a differential signal driver capable of operating at a high speed at a low voltage of 1.8V. The differential signal driver includes: a differential-signal driving circuit for switching input differential signals and outputting a common mode voltage through first and second output nodes; and a common-mode feedback circuit for providing a predetermined current to the differential-signal driving circuit or receiving a predetermined current from the differential-signal driving circuit in response to the common mode voltage. The differential-signal driving circuit includes a common-mode voltage output circuit for connecting the first output node to the second output node and generating the common mode voltage of the differential-signal driving circuit. The differential input signals are received through two bipolar transistors.

摘要翻译： 提供能够以1.8V的低电压高速运行的差分信号驱动器。 差分信号驱动器包括：差分信号驱动电路，用于切换输入差分信号并通过第一和第二输出节点输出共模电压; 以及共模反馈电路，用于响应于共模电压，向差分信号驱动电路提供预定电流或从差分信号驱动电路接收预定电流。 差分信号驱动电路包括用于将第一输出节点连接到第二输出节点并产生差动信号驱动电路的共模电压的共模电压输出电路。 差分输入信号通过两个双极晶体管接收。

公开(公告)号：US20080128817A1

公开(公告)日：2008-06-05

申请号：US12018317

申请日：2008-01-23

申请人： Kwi Dong KIM ,  Chong Ki KWON ,  Jong Dae KIM

发明人： Kwi Dong KIM ,  Chong Ki KWON ,  Jong Dae KIM

IPC分类号： H01L23/62

CPC分类号： H01L29/7436 ,  H01L29/749 ,  H01L29/87 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided is an electrostatic discharge (ESD) protection circuit using a silicon controlled rectifier (SCR), which is applied to a semiconductor integrated circuit (IC). A semiconductor substrate has a triple well structure such that a bias is applied to a p-well corresponding to a substrate of a ggNMOS device. Thus, a trigger voltage of the SCR is reduced. In addition, two discharge paths are formed using two SCRs including PNP and NPN bipolar transistors. As a result, the ESD protection circuit can have greater discharge capacity.

摘要翻译： 提供了一种应用于半导体集成电路（IC）的使用可控硅整流器（SCR）的静电放电（ESD）保护电路。 半导体衬底具有三重阱结构，使得偏置被施加到对应于ggNMOS器件的衬底的p阱。 因此，SCR的触发电压降低。 此外，使用包括PNP和NPN双极晶体管的两个SCR形成两个放电路径。 因此，ESD保护电路可以具有更大的放电容量。

公开(公告)号：US20120033511A1

公开(公告)日：2012-02-09

申请号：US13276480

申请日：2011-10-19

申请人： Kwi Dong KIM

发明人： Kwi Dong KIM

IPC分类号： G11C7/22

CPC分类号： G11C7/1039 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1069 ,  G11C7/1078 ,  G11C7/1096 ,  G11C7/22 ,  G11C7/222

摘要： A control circuit for a read operation of a SERDES (SERializer and DESeriallizer) type semiconductor memory apparatus is disclosed that includes a first line driver configured to output a portion of a output signals from sense amplifier according to a first delay signal; a second line driver configured to output a rest of the output signals from the sense amplifier according to a second delay signal; and a first delay unit configured to output a second delay signal synchronized with a clock to the second line driver.

摘要翻译： 公开了一种用于SERDES（串联器和解调器）型半导体存储器件的读取操作的控制电路，其包括：第一线驱动器，被配置为根据第一延迟信号输出来自读出放大器的输出信号的一部分; 第二线驱动器，被配置为根据第二延迟信号从读出放大器输出剩余的输出信号; 以及第一延迟单元，被配置为将与时钟同步的第二延迟信号输出到第二线路驱动器。

公开(公告)号：US20090323449A1

公开(公告)日：2009-12-31

申请号：US12535069

申请日：2009-08-04

申请人： Kwi Dong KIM

发明人： Kwi Dong KIM

IPC分类号： G11C7/00 ,  G11C7/02 ,  G11C11/24

CPC分类号： G11C11/406 ,  G11C7/04 ,  G11C11/40615 ,  G11C11/40626 ,  G11C2211/4061 ,  G11C2211/4068

摘要： The present invention relates to a circuit and a method for controlling a self-refresh cycle of a dynamic random access memory or DRAM. A cell voltage is directly detected so that a self-refresh cycle can be variably controlled. Detectors each detecting whether or not a voltage charged into a capacitor of a detection cell drops to or below a reference voltage and outputs a detection signal. A pulse generator generates a self-refresh pulse while being linked with an enabled detection signal of the plurality of detectors. A self-refresh cycle can be variably controlled and set to be suitable for the charging capacity of a cell. The detection cell is adapted to the change of the charging capacity of the cell in accordance with a change in temperature.

摘要翻译： 本发明涉及用于控制动态随机存取存储器或DRAM的自刷新周期的电路和方法。 直接检测电池电压，使得可以可变地控制自刷新周期。 检测器各自检测充电到检测单元的电容器中的电压是否下降到或低于参考电压，并输出检测信号。 脉冲发生器在与多个检测器的使能检测信号链接的同时产生自刷新脉冲。 自刷新周期可以被可变地控制并且设置成适合于电池的充电容量。 检测单元根据温度的变化适应电池的充电容量的变化。

公开(公告)号：US20080129338A1

公开(公告)日：2008-06-05

申请号：US11943031

申请日：2007-11-20

申请人： Min Hyung CHO ,  Kwi Dong KIM ,  Chong Ki KWON

发明人： Min Hyung CHO ,  Kwi Dong KIM ,  Chong Ki KWON

IPC分类号： H03K19/0948 ,  H03K19/0185

CPC分类号： H03K19/018528 ,  H03K19/0948

摘要： Provided is a high-speed asynchronous digital signal level conversion circuit converting an input signal of a first voltage level into a signal of a second voltage level. The conversion circuit is able to operate at high speed by connecting first and second nodes, at which the input signal of the first voltage level is converted to the signal of the second voltage level, to a second power source voltage of the second voltage level for fast voltage level conversion when the voltage level of the input signal is changed.

摘要翻译： 提供了将第一电压电平的输入信号转换为第二电压电平的信号的高速异步数字信号电平转换电路。 转换电路能够通过将第一和第二节点（第一电压电平的输入信号被转换为第二电压电平的信号）连接到第二电压电平的第二电源电压， 当输入信号的电压电平改变时，进行快速电压电平转换。