公开(公告)号：US07511581B2

公开(公告)日：2009-03-31

申请号：US11634004

申请日：2006-12-05

申请人： Ja Yol Lee ,  Kwi Dong Kim ,  Chong Ki Kwon ,  Jong Dae Kim ,  Sang Heung Lee

发明人： Ja Yol Lee ,  Kwi Dong Kim ,  Chong Ki Kwon ,  Jong Dae Kim ,  Sang Heung Lee

IPC分类号： H03L7/00

CPC分类号： H03K23/667 ,  H03L7/0898 ,  H03L7/093 ,  H03L7/099 ,  H03L7/193

摘要： A wide-band multimode frequency synthesizer using a Phase Locked Loop (PLL) is provided. The multiband frequency synthesizer includes a multimode prescaler, a phase detector/a charge pump, a swallow type frequency divider, and a switching bank LC tuning voltage-controlled oscillator having wide-band and low phase noise characteristics. The multimode prescaler operates in five modes and divides a signal up to 12 GHz. The wide-band frequency synthesizer can be used in various fields such as WLAN/HYPERLAN/DSRC/UWB systems that operate in the frequency range from 2 GHz to 9 GHz. The wide-band multimode frequency synthesizer includes a frequency/phase detector for comparing a frequency and phase of a reference high-frequency signal with a frequency and phase of a feedback high-frequency signal; a charge pump for producing an output current corresponding to the result of the comparison performed by the frequency/phase detector; a loop filter for producing an output voltage corresponding to an accumulated value of the output current of the charge pump; a voltage-controlled oscillator for generating an oscillation signal having a frequency corresponding to the output voltage of the loop filter; and a variable frequency divider for dividing an output signal of the voltage-controlled oscillator by a designated integer value, and outputting the result as a feedback signal, wherein at lease two of an amount of unit pumping charges of the charge pump, an RLC value of the loop filter, an RLC value of the voltage-controlled oscillator, and a divisor value of the variable frequency divider are controlled according to a band.

摘要翻译： 提供了使用锁相环（PLL）的宽带多模频率合成器。 多频率频率合成器包括多模预分频器，相位检测器/电荷泵，燕子式分频器和具有宽带和低相位噪声特性的开关组LC调谐压控振荡器。 多模预分频器以五种模式工作，并将信号分为12 GHz。 宽带频率合成器可用于各种领域，例如在2 GHz至9 GHz频率范围内工作的WLAN / HYPERLAN / DSRC / UWB系统。 宽带多模频率合成器包括用于将参考高频信号的频率和相位与反馈高频信号的频率和相位进行比较的频率/相位检测器; 用于产生与由频率/相位检测器执行的比较结果相对应的输出电流的电荷泵; 环路滤波器，用于产生与电荷泵的输出电流的累积值相对应的输出电压; 用于产生具有与环路滤波器的输出电压对应的频率的振荡信号的压控振荡器; 以及可变分频器，用于将压控振荡器的输出信号除以指定的整数值，并输出该结果作为反馈信号，其中至少两个电荷泵的单位泵送电荷，RLC值 根据频带控制环路滤波器的电压控制振荡器的RLC值和可变分频器的除数值。

公开(公告)号：US20080136464A1

公开(公告)日：2008-06-12

申请号：US11933025

申请日：2007-10-31

申请人： Kwi Dong KIM ,  Chong Ki Kwon ,  Jong Dae Kim

发明人： Kwi Dong KIM ,  Chong Ki Kwon ,  Jong Dae Kim

IPC分类号： H03K3/00 ,  H01L21/8249

CPC分类号： H01L21/8249 ,  H01L27/0623 ,  H01L29/41708 ,  H01L29/7322 ,  H03F3/45085 ,  H03F3/45179 ,  H03F3/45502 ,  H03F2203/45008 ,  H03F2203/45082 ,  H03F2203/45418 ,  H03F2203/45424 ,  H03K5/003 ,  H03K19/01 ,  H04L25/0276 ,  H04L25/0282

摘要： Provided is a differential signal driver capable of operating at a high speed at a low voltage of 1.8V. The differential signal driver includes: a differential-signal driving circuit for switching input differential signals and outputting a common mode voltage through first and second output nodes; and a common-mode feedback circuit for providing a predetermined current to the differential-signal driving circuit or receiving a predetermined current from the differential-signal driving circuit in response to the common mode voltage. The differential-signal driving circuit includes a common-mode voltage output circuit for connecting the first output node to the second output node and generating the common mode voltage of the differential-signal driving circuit. The differential input signals are received through two bipolar transistors.

摘要翻译： 提供能够以1.8V的低电压高速运行的差分信号驱动器。 差分信号驱动器包括：差分信号驱动电路，用于切换输入差分信号并通过第一和第二输出节点输出共模电压; 以及共模反馈电路，用于响应于共模电压，向差分信号驱动电路提供预定电流或从差分信号驱动电路接收预定电流。 差分信号驱动电路包括用于将第一输出节点连接到第二输出节点并产生差动信号驱动电路的共模电压的共模电压输出电路。 差分输入信号通过两个双极晶体管接收。

公开(公告)号：US07268623B2

公开(公告)日：2007-09-11

申请号：US11292673

申请日：2005-12-02

申请人： Kwi Dong Kim ,  Chong Ki Kwon ,  Jong Dae Kim

发明人： Kwi Dong Kim ,  Chong Ki Kwon ,  Jong Dae Kim

IPC分类号： H03F3/45

CPC分类号： H03F3/45748 ,  H03F2200/513 ,  H03F2203/45082 ,  H03F2203/45644

摘要： Provided are a low voltage differential signal driver circuit and a method for controlling the same. The differential signal driver circuit includes: a differential amplification signal generator disposed between a power supply voltage terminal and a ground terminal, and outputting first and second differential amplification signals to first and second output terminals in response to first and second differential input signals, respectively; a common mode voltage generator for generating a common mode voltage in response to DC (direct current) offset voltages of the first and second differential amplification signals; and a variable load portion for controlling a resistance between the power supply voltage terminal and the first output terminal and a resistance between the power supply voltage terminal and the second output terminal in response to the common mode voltage such that the first and second differential amplification signals have constant DC offset voltages.

摘要翻译： 提供了一种低电压差分信号驱动电路及其控制方法。 差分信号驱动电路包括：差分放大信号发生器，其设置在电源电压端和接地端之间，并分别响应于第一和第二差分输入信号而将第一和第二差分放大信号输出到第一和第二输出端; 共模电压发生器，用于响应于第一和第二差分放大信号的DC（直流）偏移电压产生共模电压; 以及可变负载部分，用于响应于共模电压来控制电源电压端子和第一输出端子之间的电阻以及电源电压端子和第二输出端子之间的电阻，使得第一和第二差分放大信号 具有恒定的直流偏移电压。

公开(公告)号：US07532146B2

公开(公告)日：2009-05-12

申请号：US11903476

申请日：2007-09-20

申请人： Young Deuk Jeon ,  Seung Chul Lee ,  Kwi Dong Kim ,  Chong Ki Kwon ,  Jong Dae Kim

发明人： Young Deuk Jeon ,  Seung Chul Lee ,  Kwi Dong Kim ,  Chong Ki Kwon ,  Jong Dae Kim

IPC分类号： H03M1/38

CPC分类号： H03M1/0682 ,  H03M1/167 ,  H03M1/804

摘要： Provided is a multi-bit pipeline analog-to-digital converter (ADC) having a merged capacitor switching structure. In a multiplying digital-to-analog converter (MDAC) used in the multi-bit pipeline ADC, switches are connected between the bottom plates of respective differential capacitors, thereby constantly maintaining a uniform input common mode voltage regardless of an input digital code. Thus, it is possible to improve the operating speed and performance of the MDAC.

摘要翻译： 提供了具有合并电容器开关结构的多位流水线模数转换器（ADC）。 在多位流水线ADC中使用的乘法数模转换器（MDAC）中，开关连接在各个差分电容器的底板之间，从而不管输入数字代码如何，始终保持均匀的输入共模电压。 因此，可以提高MDAC的操作速度和性能。

公开(公告)号：US20070126616A1

公开(公告)日：2007-06-07

申请号：US11591740

申请日：2006-11-02

申请人： Min Hyung Cho ,  Chong Ki Kwon ,  Jong Dae Kim ,  Kwi Dong Kim

发明人： Min Hyung Cho ,  Chong Ki Kwon ,  Jong Dae Kim ,  Kwi Dong Kim

IPC分类号： H03M1/66

CPC分类号： H03M1/0673 ,  H03M1/742

摘要： Provided is a digital-to-analog converter converting a digital signal into an analog signal. The digital-to-analog converter includes a decoder for selecting a current source from digital inputs, a current switch driver for driving a current switch of the current source, and a random selection switch disposed between the decoder and the current switch driver, and randomly resetting a connection relationship between outputs of the decoder and inputs of the current switch driver every clock. According to the present invention, the linearity of the digital-to-analog converter may be enhanced by changing the current source selected every clock signal to compensate for non-linearity of the digital-to-analog converter according to the spatial arrangement of the current sources.

摘要翻译： 提供了将数字信号转换为模拟信号的数模转换器。 数模转换器包括用于从数字输入端选择电流源的解码器，用于驱动电流源的电流开关的电流开关驱动器，以及设置在解码器和电流开关驱动器之间的随机选择开关，以及随机 在每个时钟复位解码器的输出和当前开关驱动器的输入之间的连接关系。 根据本发明，可以通过改变每个时钟信号选择的电流源来增强数模转换器的线性度，以根据电流的空间布置补偿数模转换器的非线性 来源。

公开(公告)号：US20090072919A1

公开(公告)日：2009-03-19

申请号：US12195185

申请日：2008-08-20

申请人： Hui Dong Lee ,  Kwi Dong Kim ,  Chong Ki Kwon ,  Jong Dae Kim

发明人： Hui Dong Lee ,  Kwi Dong Kim ,  Chong Ki Kwon ,  Jong Dae Kim

IPC分类号： H03B5/12

CPC分类号： H03B5/1215 ,  H03B5/1253 ,  H03B5/1256 ,  H03B5/1293

摘要： Provided is a voltage-controlled oscillator with a wide oscillation frequency range and linear characteristics, which can linearly change an oscillation frequency versus control voltage due to a variable capacitance range increased by several MOS transistors additionally connected to an LC resonant circuit, and can control the oscillation frequency range by adjusting numbers, widths, lengths and operation regions of the MOS transistors. Thus, the voltage-controlled oscillator with a wide oscillation frequency range and linear control voltage-oscillation frequency characteristics without using a switching device can be implemented.

摘要翻译： 提供一种具有宽振荡频率范围和线性特性的压控振荡器，其可以由另外连接到LC谐振电路的多个MOS晶体管增加的可变电容范围而使振荡频率与控制电压线性地改变，并且可以控制 通过调整MOS晶体管的数量，宽度，长度和操作区域来实现振荡频率范围。 因此，可以实现具有宽振荡频率范围的压控振荡器和不使用开关装置的线性控制电压 - 振荡频率特性。

公开(公告)号：US20060125533A1

公开(公告)日：2006-06-15

申请号：US11292673

申请日：2005-12-02

申请人： Kwi Dong Kim ,  Chong Ki Kwon ,  Jong Dae Kim

发明人： Kwi Dong Kim ,  Chong Ki Kwon ,  Jong Dae Kim

IPC分类号： H03B1/00

CPC分类号： H03F3/45748 ,  H03F2200/513 ,  H03F2203/45082 ,  H03F2203/45644

摘要： Provided are a low voltage differential signal driver circuit and a method for controlling the same. The differential signal driver circuit includes: a differential amplification signal generator disposed between a power supply voltage terminal and a ground terminal, and outputting first and second differential amplification signals to first and second output terminals in response to first and second differential input signals, respectively; a common mode voltage generator for generating a common mode voltage in response to DC (direct current) offset voltages of the first and second differential amplification signals; and a variable load portion for controlling a resistance between the power supply voltage terminal and the first output terminal and a resistance between the power supply voltage terminal and the second output terminal in response to the common mode voltage such that the first and second differential amplification signals have constant DC offset voltages.

摘要翻译： 提供了一种低电压差分信号驱动电路及其控制方法。 差分信号驱动电路包括：差分放大信号发生器，其设置在电源电压端和接地端之间，并分别响应于第一和第二差分输入信号而将第一和第二差分放大信号输出到第一和第二输出端; 共模电压发生器，用于响应于第一和第二差分放大信号的DC（直流）偏移电压产生共模电压; 以及可变负载部分，用于响应于共模电压来控制电源电压端子和第一输出端子之间的电阻以及电源电压端子和第二输出端子之间的电阻，使得第一和第二差分放大信号 具有恒定的直流偏移电压。

公开(公告)号：US07576961B2

公开(公告)日：2009-08-18

申请号：US12018317

申请日：2008-01-23

申请人： Kwi Dong Kim ,  Chong Ki Kwon ,  Jong Dae Kim

发明人： Kwi Dong Kim ,  Chong Ki Kwon ,  Jong Dae Kim

IPC分类号： H02H9/00 ,  H01L23/62

CPC分类号： H01L29/7436 ,  H01L29/749 ,  H01L29/87 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided is an electrostatic discharge (ESD) protection circuit using a silicon controlled rectifier (SCR), which is applied to a semiconductor integrated circuit (IC). A semiconductor substrate has a triple well structure such that a bias is applied to a p-well corresponding to a substrate of a ggNMOS device. Thus, a trigger voltage of the SCR is reduced. In addition, two discharge paths are formed using two SCRs including PNP and NPN bipolar transistors. As a result, the ESD protection circuit can have greater discharge capacity.

摘要翻译： 提供了一种应用于半导体集成电路（IC）的使用可控硅整流器（SCR）的静电放电（ESD）保护电路。 半导体衬底具有三重阱结构，使得偏置被施加到对应于ggNMOS器件的衬底的p阱。 因此，SCR的触发电压降低。 此外，使用包括PNP和NPN双极晶体管的两个SCR形成两个放电路径。 因此，ESD保护电路可以具有更大的放电容量。

公开(公告)号：US07545301B2

公开(公告)日：2009-06-09

申请号：US11950481

申请日：2007-12-05

申请人： Yi Gyeong Kim ,  Kwi Dong Kim ,  Chong Ki Kwon ,  Jong Dae Kim

发明人： Yi Gyeong Kim ,  Kwi Dong Kim ,  Chong Ki Kwon ,  Jong Dae Kim

IPC分类号： H03M3/00

CPC分类号： H03M3/374 ,  H03M3/338 ,  H03M3/424 ,  H03M3/45 ,  H03M3/452 ,  H03M3/454

摘要： A delta-sigma modulator having a first integrator for integrating an input signal; an analog-to-digital converter for converting the integrated signal into a digital signal; a delay circuit for delaying an output signal of the analog-to-digital converter; and a differential delay circuit for differentially delaying the output signal of the analog-to-digital converter. More particularly, the delta-sigma modulator has low distortion characteristics suitable for multi-bit fast operation, wherein a feedback signal is delayed by one clock period through the delay circuit and the differential delay circuit.

摘要翻译： 一种Δ-Σ调制器，具有用于积分输入信号的第一积分器; 用于将积分信号转换为数字信号的模拟 - 数字转换器; 延迟电路，用于延迟模数转换器的输出信号; 以及用于差分地延迟模数转换器的输出信号的差分延迟电路。 更具体地，Δ-Σ调制器具有适合于多位快速操作的低失真特性，其中通过延迟电路和差分延迟电路将反馈信号延迟一个时钟周期。

公开(公告)号：US07342281B2

公开(公告)日：2008-03-11

申请号：US11294255

申请日：2005-12-05

申请人： Kwi Dong Kim ,  Chong Ki Kwon ,  Jong Dae Kim

发明人： Kwi Dong Kim ,  Chong Ki Kwon ,  Jong Dae Kim

IPC分类号： H01L23/62

CPC分类号： H01L29/7436 ,  H01L29/749 ,  H01L29/87 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided is an electrostatic discharge (ESD) protection circuit using a silicon controlled rectifier (SCR), which is applied to a semiconductor integrated circuit (IC). A semiconductor substrate has a triple well structure such that a bias is applied to a p-well corresponding to a substrate of a ggNMOS device. Thus, a trigger voltage of the SCR is reduced. In addition, two discharge paths are formed using two SCRs including PNP and NPN bipolar transistors. As a result, the ESD protection circuit can have greater discharge capacity.

摘要翻译： 提供了一种应用于半导体集成电路（IC）的使用可控硅整流器（SCR）的静电放电（ESD）保护电路。 半导体衬底具有三重阱结构，使得偏置被施加到对应于ggNMOS器件的衬底的p阱。 因此，SCR的触发电压降低。 此外，使用包括PNP和NPN双极晶体管的两个SCR形成两个放电路径。 因此，ESD保护电路可以具有更大的放电容量。