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    Dynamic element-matching method, multi-bit DAC using the method, and delta-sigma modulator and delta-sigma DAC including the multi-bit DAC
    1.
    发明授权
    Dynamic element-matching method, multi-bit DAC using the method, and delta-sigma modulator and delta-sigma DAC including the multi-bit DAC 有权
    动态元件匹配方法，使用该方法的多位DAC，以及包括多位DAC的Δ-Σ调制器和Δ-ΣDAC

    公开(公告)号：US07719455B2

    公开(公告)日：2010-05-18

    申请号：US12195232

    申请日：2008-08-20

    申请人： Yi Gyeong Kim ,  Min Hyung Cho ,  Chong Ki Kwon

    发明人： Yi Gyeong Kim ,  Min Hyung Cho ,  Chong Ki Kwon

    IPC分类号： H03M1/66

    CPC分类号： H03M1/0665 ,  H03M1/74 ,  H03M3/464 ,  H03M3/502

    摘要： Provided are a dynamic element-matching method, a multi-bit Digital-to-Analog Converter (DAC), and a delta-sigma modulator with the multi-bit DAC and delta-sigma DAC with the multi-bit DAC. The dynamic element-matching method relates to preventing periodic signal components (in-band tones) from being generated from a delta-sigma modulator of a delta-sigma Analog-to-Digital Converter (ADC) and a multi-bit DAC used in a delta-sigma DAC. Unit elements are selected in a new sequence according to a simple algorithm every time that each of unit elements is selected once, and thus the unit elements are not periodically used. Consequently, it is possible to prevent in-band tones caused by a conventional Data Weighted Averaging (DWA) algorithm.

    摘要翻译： 提供了动态元件匹配方法，多位数模转换器（DAC）和具有多位DAC的多位DAC和Δ-ΣDAC的Δ-Σ调制器。 动态元件匹配方法涉及防止从Δ-Σ模数转换器（ADC）的delta-sigma调制器和用于在A-Sigma模数转换器（ADC）中使用的多位DAC的周期性信号分量（带内音调） Δ-ΣDAC。 每次选择一个单位元素一次时，根据简单算法以新的顺序选择单位元素，因此单位元素不被周期性地使用。 因此，可以防止由传统的数据加权平均（DWA）算法引起的带内音调。

    Multi-bit pipeline analog-to-digital converter capable of altering operating mode
    3.
    发明授权
    Multi-bit pipeline analog-to-digital converter capable of altering operating mode 有权
    能够改变操作模式的多位流水线模数转换器

    公开(公告)号：US07486216B2

    公开(公告)日：2009-02-03

    申请号：US11707614

    申请日：2007-02-16

    申请人： Seung Chul Lee ,  Young Deuk Jeon ,  Kwi Dong Kim ,  Chong Ki Kwon

    发明人： Seung Chul Lee ,  Young Deuk Jeon ,  Kwi Dong Kim ,  Chong Ki Kwon

    IPC分类号： H03M1/38

    CPC分类号： H03M1/002 ,  H03M1/007 ,  H03M1/069 ,  H03M1/168

    摘要： Provided is a multi-bit pipeline analog-to-digital converter (ADC) capable of altering an operating mode. The ADC includes: a sample-and-hold amplifier (SHA) for sampling and holding an input analog voltage; an n+1 number of B-bit flash ADCs for receiving an analog signal and converting the analog signal into a digital signal to output the digital signal; an n number of B-bit multiplying digital-to-analog converters (MDACs) for converting a difference between the digital signal output from the B-bit flash ADC and the front-stage output signal into an analog signal to output the analog signal to the next stage; and a mode control circuit for generating n-bit control signals to control the B-bit flash ADC and the B-bit MDAC according to required resolution and operating frequency. In the multi-bit pipeline ADC, an operating mode is altered by controlling the number of stages in a pipeline and a signal path according to required resolution and operating frequency, so that power consumption can be minimized under the corresponding operating condition and signals can be processed in a variety of ways.

    摘要翻译： 提供了能够改变操作模式的多位流水线模数转换器（ADC）。 ADC包括：采样和保持放大器（SHA），用于采样和保持输入模拟电压; n + 1个B位闪存ADC，用于接收模拟信号并将模拟信号转换成数字信号以输出数字信号; 用于将从B位闪存ADC输出的数字信号与前级输出信号之间的差异转换为模拟信号的n个B位乘法数模转换器（MDAC），以将模拟信号输出到 下一阶段; 以及用于根据需要的分辨率和工作频率产生n位控制信号以控制B位闪存ADC和B位MDAC的模式控制电路。 在多位流水线ADC中，通过根据需要的分辨率和工作频率控制流水线中的级数和信号路径来改变操作模式，从而可以在相应的操作条件下使功耗最小化，信号可以是 以各种方式处理。

    ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT USING TRIPLE WELLED SILICON CONTROLLED RECTIFIER
    4.
    发明申请
    ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT USING TRIPLE WELLED SILICON CONTROLLED RECTIFIER 有权
    静电放电保护电路，采用三重硅片控制整流器

    公开(公告)号：US20080128817A1

    公开(公告)日：2008-06-05

    申请号：US12018317

    申请日：2008-01-23

    申请人： Kwi Dong KIM ,  Chong Ki KWON ,  Jong Dae KIM

    发明人： Kwi Dong KIM ,  Chong Ki KWON ,  Jong Dae KIM

    IPC分类号： H01L23/62

    CPC分类号： H01L29/7436 ,  H01L29/749 ,  H01L29/87 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Provided is an electrostatic discharge (ESD) protection circuit using a silicon controlled rectifier (SCR), which is applied to a semiconductor integrated circuit (IC). A semiconductor substrate has a triple well structure such that a bias is applied to a p-well corresponding to a substrate of a ggNMOS device. Thus, a trigger voltage of the SCR is reduced. In addition, two discharge paths are formed using two SCRs including PNP and NPN bipolar transistors. As a result, the ESD protection circuit can have greater discharge capacity.

    摘要翻译： 提供了一种应用于半导体集成电路（IC）的使用可控硅整流器（SCR）的静电放电（ESD）保护电路。 半导体衬底具有三重阱结构，使得偏置被施加到对应于ggNMOS器件的衬底的p阱。 因此，SCR的触发电压降低。 此外，使用包括PNP和NPN双极晶体管的两个SCR形成两个放电路径。 因此，ESD保护电路可以具有更大的放电容量。

    Dynamically linearized digital-to-analog converter
    5.
    发明申请
    Dynamically linearized digital-to-analog converter 审中-公开
    动态线性化数模转换器

    公开(公告)号：US20070126616A1

    公开(公告)日：2007-06-07

    申请号：US11591740

    申请日：2006-11-02

    申请人： Min Hyung Cho ,  Chong Ki Kwon ,  Jong Dae Kim ,  Kwi Dong Kim

    发明人： Min Hyung Cho ,  Chong Ki Kwon ,  Jong Dae Kim ,  Kwi Dong Kim

    IPC分类号： H03M1/66

    CPC分类号： H03M1/0673 ,  H03M1/742

    摘要： Provided is a digital-to-analog converter converting a digital signal into an analog signal. The digital-to-analog converter includes a decoder for selecting a current source from digital inputs, a current switch driver for driving a current switch of the current source, and a random selection switch disposed between the decoder and the current switch driver, and randomly resetting a connection relationship between outputs of the decoder and inputs of the current switch driver every clock. According to the present invention, the linearity of the digital-to-analog converter may be enhanced by changing the current source selected every clock signal to compensate for non-linearity of the digital-to-analog converter according to the spatial arrangement of the current sources.

    摘要翻译： 提供了将数字信号转换为模拟信号的数模转换器。 数模转换器包括用于从数字输入端选择电流源的解码器，用于驱动电流源的电流开关的电流开关驱动器，以及设置在解码器和电流开关驱动器之间的随机选择开关，以及随机 在每个时钟复位解码器的输出和当前开关驱动器的输入之间的连接关系。 根据本发明，可以通过改变每个时钟信号选择的电流源来增强数模转换器的线性度，以根据电流的空间布置补偿数模转换器的非线性 来源。

    High-speed asynchronous digital signal level conversion circuit
    6.
    发明授权
    High-speed asynchronous digital signal level conversion circuit 失效
    高速异步数字信号电平转换电路

    公开(公告)号：US07663403B2

    公开(公告)日：2010-02-16

    申请号：US11943031

    申请日：2007-11-20

    申请人： Min Hyung Cho ,  Kwi Dong Kim ,  Chong Ki Kwon

    发明人： Min Hyung Cho ,  Kwi Dong Kim ,  Chong Ki Kwon

    IPC分类号： H03K19/0175

    CPC分类号： H03K19/018528 ,  H03K19/0948

    摘要： Provided is a high-speed asynchronous digital signal level conversion circuit converting an input signal of a first voltage level into a signal of a second voltage level. The conversion circuit is able to operate at high speed by connecting first and second nodes, at which the input signal of the first voltage level is converted to the signal of the second voltage level, to a second power source voltage of the second voltage level for fast voltage level conversion when the voltage level of the input signal is changed.

    摘要翻译： 提供了将第一电压电平的输入信号转换为第二电压电平的信号的高速异步数字信号电平转换电路。 转换电路能够通过将第一和第二节点（第一电压电平的输入信号被转换为第二电压电平的信号）连接到第二电压电平的第二电源电压， 当输入信号的电压电平改变时，进行快速电压电平转换。

    Electrostatic discharge protection circuit using triple welled silicon controlled rectifier
    7.
    发明授权
    Electrostatic discharge protection circuit using triple welled silicon controlled rectifier 有权
    静电放电保护电路采用三芯硅控整流器

    公开(公告)号：US07576961B2

    公开(公告)日：2009-08-18

    申请号：US12018317

    申请日：2008-01-23

    申请人： Kwi Dong Kim ,  Chong Ki Kwon ,  Jong Dae Kim

    发明人： Kwi Dong Kim ,  Chong Ki Kwon ,  Jong Dae Kim

    IPC分类号： H02H9/00 ,  H01L23/62

    CPC分类号： H01L29/7436 ,  H01L29/749 ,  H01L29/87 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Provided is an electrostatic discharge (ESD) protection circuit using a silicon controlled rectifier (SCR), which is applied to a semiconductor integrated circuit (IC). A semiconductor substrate has a triple well structure such that a bias is applied to a p-well corresponding to a substrate of a ggNMOS device. Thus, a trigger voltage of the SCR is reduced. In addition, two discharge paths are formed using two SCRs including PNP and NPN bipolar transistors. As a result, the ESD protection circuit can have greater discharge capacity.

    摘要翻译： 提供了一种应用于半导体集成电路（IC）的使用可控硅整流器（SCR）的静电放电（ESD）保护电路。 半导体衬底具有三重阱结构，使得偏置被施加到对应于ggNMOS器件的衬底的p阱。 因此，SCR的触发电压降低。 此外，使用包括PNP和NPN双极晶体管的两个SCR形成两个放电路径。 因此，ESD保护电路可以具有更大的放电容量。

    Multi-bit delta-sigma modulator
    8.
    发明授权
    Multi-bit delta-sigma modulator 有权
    多位delta-Σ调制器

    公开(公告)号：US07545301B2

    公开(公告)日：2009-06-09

    申请号：US11950481

    申请日：2007-12-05

    申请人： Yi Gyeong Kim ,  Kwi Dong Kim ,  Chong Ki Kwon ,  Jong Dae Kim

    发明人： Yi Gyeong Kim ,  Kwi Dong Kim ,  Chong Ki Kwon ,  Jong Dae Kim

    IPC分类号： H03M3/00

    CPC分类号： H03M3/374 ,  H03M3/338 ,  H03M3/424 ,  H03M3/45 ,  H03M3/452 ,  H03M3/454

    摘要： A delta-sigma modulator having a first integrator for integrating an input signal; an analog-to-digital converter for converting the integrated signal into a digital signal; a delay circuit for delaying an output signal of the analog-to-digital converter; and a differential delay circuit for differentially delaying the output signal of the analog-to-digital converter. More particularly, the delta-sigma modulator has low distortion characteristics suitable for multi-bit fast operation, wherein a feedback signal is delayed by one clock period through the delay circuit and the differential delay circuit.

    摘要翻译： 一种Δ-Σ调制器，具有用于积分输入信号的第一积分器; 用于将积分信号转换为数字信号的模拟 - 数字转换器; 延迟电路，用于延迟模数转换器的输出信号; 以及用于差分地延迟模数转换器的输出信号的差分延迟电路。 更具体地，Δ-Σ调制器具有适合于多位快速操作的低失真特性，其中通过延迟电路和差分延迟电路将反馈信号延迟一个时钟周期。

    DYNAMIC ELEMENT-MATCHING METHOD, MULTI-BIT DAC USING THE METHOD, AND DELTA-SIGMA MODULATOR AND DELTA-SIGMA DAC INCLUDING THE MULTI-BIT DAC
    9.
    发明申请
    DYNAMIC ELEMENT-MATCHING METHOD, MULTI-BIT DAC USING THE METHOD, AND DELTA-SIGMA MODULATOR AND DELTA-SIGMA DAC INCLUDING THE MULTI-BIT DAC 有权
    使用该方法的动态元件匹配方法，多位DAC，以及包括多位DAC的DELTA-SIGMA调制器和DELTA-SIGMA DAC

    公开(公告)号：US20090121909A1

    公开(公告)日：2009-05-14

    申请号：US12195232

    申请日：2008-08-20

    申请人： Yi Gyeong KIM ,  Min Hyung Cho ,  Chong Ki Kwon

    发明人： Yi Gyeong KIM ,  Min Hyung Cho ,  Chong Ki Kwon

    IPC分类号： H03M3/00 ,  H03M1/66 ,  H03M1/80

    CPC分类号： H03M1/0665 ,  H03M1/74 ,  H03M3/464 ,  H03M3/502

    摘要： Provided are a dynamic element-matching method, a multi-bit Digital-to-Analog Converter (DAC), and a delta-sigma modulator with the multi-bit DAC and delta-sigma DAC with the multi-bit DAC. The dynamic element-matching method relates to preventing periodic signal components (in-band tones) from being generated from a delta-sigma modulator of a delta-sigma Analog-to-Digital Converter (ADC) and a multi-bit DAC used in a delta-sigma DAC. Unit elements are selected in a new sequence according to a simple algorithm every time that each of unit elements is selected once, and thus the unit elements are not periodically used. Consequently, it is possible to prevent in-band tones caused by a conventional Data Weighted Averaging (DWA) algorithm.

    摘要翻译： 提供了动态元件匹配方法，多位数模转换器（DAC）和具有多位DAC的多位DAC和Δ-ΣDAC的Δ-Σ调制器。 动态元件匹配方法涉及防止从Δ-Σ模数转换器（ADC）的delta-sigma调制器和用于在A-Sigma模数转换器（ADC）中使用的多位DAC的周期性信号分量（带内音调） Δ-ΣDAC。 每次选择一个单位元素一次时，根据简单算法以新的顺序选择单位元素，因此单位元素不被周期性地使用。 因此，可以防止由传统的数据加权平均（DWA）算法引起的带内音调。