Controller and operating method thereof

    公开(公告)号:US10528496B2

    公开(公告)日:2020-01-07

    申请号:US15601039

    申请日:2017-05-22

    Abstract: A controller may include a first encoder suitable for generating a first polar parity by performing a first polar encoding operation to respective first sections of an original message having a plurality of symbols, an interleaver suitable for generating an interleaved message by interleaving the original message according to first reliabilities, which are predetermined depending on locations of the respective symbols in the respective first sections in the original message, and second reliabilities, which are predetermined depending on locations of the respective symbols in the interleaved message, a second encoder suitable for generating a second polar parity by performing a second polar encoding operation to respective second sections included in the interleaved message and a memory interface suitable for storing the original message, the first polar parity and the second polar parity into a memory.

    Memory system for interference compensation and operating method thereof

    公开(公告)号:US11158386B2

    公开(公告)日:2021-10-26

    申请号:US16848578

    申请日:2020-04-14

    Abstract: A memory system includes a memory device including a plurality of memory cells, and a controller configured to access the plurality of memory cells. The controller includes a data read block configured to read first data from one or more pages included in first memory cells, determine a target memory cell subject to a compensation based on the first data, and read second data from one or more pages of second memory cells adjacent to the target memory cell, and an equalizer configured to convert the second data into symbol interfering data, check a probability of the first data from a lookup table according to the symbol interfering data, and determine the compensation on the first data based on the probability.

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