公开(公告)号：US12112813B2

公开(公告)日：2024-10-08

申请号：US17847056

申请日：2022-06-22

Applicant: SK hynix Inc. ,  Korea Advanced Institute of Science and Technology

Inventor： Sunyoung Jo ,  Jungwuk Park ,  Younghyun Park ,  Sang Ho Yun ,  Jaekyun Moon

IPC: G11C16/34 ,  G06N3/045 ,  G11C16/28

CPC classification number: G11C16/3431 ,  G06N3/045 ,  G11C16/28

Abstract: A device includes a threshold voltage distribution estimation network configured to generate an estimated distribution using a feature distribution and read trial information, a set of feature distributions generated from a plurality of threshold voltage distributions for a plurality of pages of a memory device, and a read reference voltage estimation network configured to generate a read reference voltage from the estimated distribution. The read trial information includes a read trial vector and an output value, the output value being generated by applying the read trial vector to a threshold voltage distribution for a page to be read among the plurality of threshold voltage distributions.

公开(公告)号：US12248683B2

公开(公告)日：2025-03-11

申请号：US17994080

申请日：2022-11-25

Applicant: SK hynix Inc.

Inventor： Sang Ho Yun ,  Jang Seob Kim

IPC: G11C29/50 ,  G06F3/06

Abstract: A storage device includes a memory device and a controller. The memory device includes a memory region which includes a first sub-region and a second sub-region. The controller reads assist data from a plurality of memory cells according to an assist read voltage during a read voltage adjusting operation on the first sub-region as a target sub-region, and re-utilizes the read assist data during the read voltage adjusting operation on the second sub-region as the target sub-region.

公开(公告)号：US11450400B2

公开(公告)日：2022-09-20

申请号：US17074097

申请日：2020-10-19

Applicant: SK hynix Inc.

Inventor： Sang Ho Yun ,  Soon Young Kang ,  Dae Sung Kim

IPC: G11C29/42 ,  G11C29/12 ,  G11C29/50 ,  H03M13/11 ,  H03M13/29

Abstract: The controller that controls a memory device includes: a processor suitable for controlling the memory device to perform a first soft read operation by using first soft read voltages; and an error correction code (ECC) codec suitable for performing a first soft decision decoding operation based on first soft read data obtained through the first soft read operation, wherein the processor controls the memory device to perform a second soft read operation with an additional read voltage, of second soft read voltages, that is different than any of the first soft read voltages and which is determined based on the first soft read data, according to whether the first soft decision decoding operation failed, and wherein the ECC codec performs a second soft decision decoding operation based on the first soft read data and second soft read data obtained through the second soft read operation.

公开(公告)号：US12283307B2

公开(公告)日：2025-04-22

申请号：US18063007

申请日：2022-12-07

Applicant: SK hynix Inc.

Inventor： Jae Yong Son ,  Nam Kyeong Kim ,  Hoon Cho ,  Hyuk Min Kwon ,  Dae Sung Kim ,  Jang Seob Kim ,  Sang Ho Yun

IPC: G11C11/56 ,  G11C11/4078 ,  G11C11/408 ,  G11C11/4096

Abstract: A storage device includes a memory including a plurality of word lines, a plurality of bit lines and a plurality of memory cells, and a controller configured to control the memory and perform a read retry operation for the memory using a read retry table. The memory includes a special block that stores a read retry table in which a plurality of read retry values are set for each of a plurality of first conditions and each of a plurality of second conditions corresponding to each of the plurality of first conditions.

公开(公告)号：US12046295B2

公开(公告)日：2024-07-23

申请号：US17528788

申请日：2021-11-17

Applicant: SK hynix Inc.

Inventor： Sang Ho Yun

IPC: G11C16/26 ,  G06F11/22 ,  G11C16/04

CPC classification number: G11C16/26 ,  G06F11/2215 ,  G11C16/0483

Abstract: The present technology includes a method of operating a controller capable of controlling a semiconductor memory device including a plurality of memory cells. The method of operating the controller includes sensing error correction failure of data read from the semiconductor memory device, generating a new read voltage for re-reading the data, determining whether the new read voltage belongs to an allowable range depending on a read voltage statistical value of previous read voltages according to which error corrections were successful on previously read data, and determining, based on a result of the determining whether the new read voltage belongs to the allowable range, a read voltage to be used in a next read operation of re-reading the data.

公开(公告)号：US12204404B2

公开(公告)日：2025-01-21

申请号：US18467731

申请日：2023-09-15

Applicant: SK hynix Inc.

Inventor： Dae Sung Kim ,  Soon Young Kang ,  Sang Ho Yun

IPC: H03M13/00 ,  G06F11/10 ,  H03M13/15

Abstract: The present technology provides a controller for controlling a memory device comprising: a hard syndrome calculator configured to generate a hard syndrome of a hard data chunk received from the memory device; a delta syndrome calculator configured to generate a delta syndrome of a delta bit data received from the memory device, the delta bit data indicating a reliability of the hard data chunk; a soft syndrome generator configured to generate a soft syndrome of the hard syndrome and the delta syndrome; a data determinator configured to select, as hard decision data, one of the hard data chunk and a soft data chunk, the selected data chunk corresponding to a syndrome having a lowest syndrome weight; and an error corrector configured to perform an ECC decoding operation on the hard decision data.

公开(公告)号：US12068046B2

公开(公告)日：2024-08-20

申请号：US17828262

申请日：2022-05-31

Applicant: SK hynix Inc.

Inventor： Jang Seob Kim ,  Sang Ho Yun

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26

CPC classification number: G11C16/3459 ,  G11C16/102 ,  G11C16/26 ,  G11C16/3404

Abstract: A storage device includes: a memory device including a plurality of memory cells, the memory device performing a read operation of reading data stored in selected memory cells among the plurality of memory cells; and a memory controller for receiving a read request from a host, and controlling the memory device to perform the read operation corresponding to the read request. The memory controller includes a read voltage inferrer for, when the read operation is completed, receiving read information on the read operation from the memory device, performing a read quality evaluation operation of evaluating the read operation based on the read information, and performing a read voltage inference operation of inferring a secondary read level corresponding to the read information according to a result of the performing the read quality evaluation operation.