公开(公告)号：US20160179611A1

公开(公告)日：2016-06-23

申请号：US14581878

申请日：2014-12-23

申请人： Thuyen Le ,  Kay Hesse ,  Uwe Steeb ,  Tian Yan Pu ,  Lars Melzer

发明人： Thuyen Le ,  Kay Hesse ,  Uwe Steeb ,  Tian Yan Pu ,  Lars Melzer

IPC分类号： G06F11/10

CPC分类号： G06F11/1012

摘要： An apparatus and method are described for performing a low overhead error checking and correction. For example, one embodiment of an electronic circuit comprises: one or more memories to store data or instructions in rows and columns, and to further store row parity data comprising a parity value associated with each row and column parity data comprising a parity value associated with each column; and error checking logic to perform a row parity check to detect if errors exist in any of the rows, wherein if an error is detected in one of the rows, the error checking and correction logic is to perform a column parity check to identify a column in which the detected error occurred; and error correction logic to correct the detected error using the detected row and column identified by the error checking logic.

摘要翻译： 描述了用于执行低开销错误检查和校正的装置和方法。 例如，电子电路的一个实施例包括：用于以行和列存储数据或指令的一个或多个存储器，并且还用于存储包括与每行和列奇偶校验数据相关联的奇偶校验值的行奇偶校验数据，其包括与 每列; 以及错误检查逻辑来执行行奇偶校验以检测是否存在任何行中的错误，其中如果在其中一行中检测到错误，则错误检查和校正逻辑是执行列奇偶校验以识别列 其中检测到的错误发生; 以及纠错逻辑，以使用由错误检查逻辑识别的检测到的行和列校正检测到的错误。

公开(公告)号：US20120072788A1

公开(公告)日：2012-03-22

申请号：US12883441

申请日：2010-09-16

申请人： Wei-Yu Chen ,  Kevin Badgett ,  Kay Hesse

发明人： Wei-Yu Chen ,  Kevin Badgett ,  Kay Hesse

IPC分类号： G11C29/36 ,  G06F11/27

CPC分类号： G11C29/36 ,  G11C29/06 ,  G11C29/28 ,  G11C2029/2602

摘要： Integrated circuits with memory built-in self test (MBIST) circuitry and methods are disclosed that employ enhanced features. In one aspect of the invention, an integrated circuit is provided having MIBST circuitry configured to serially test multiple arrays of memory elements within a component of the integrated circuit and to also conduct parallel initialization of the serially tested arrays. In another aspect of the invention, the MBST circuitry is used set the memory elements of the arrays to a first state and then to an inverse state during a burn-in operation to maintain each of the two opposing states for a desired time in order to either force a failure of the integrated circuit component or produce a pre-stressed component beyond an infancy stage.

摘要翻译： 具有存储器内置自检（MBIST）电路和方法的集成电路被公开，其采用增强的特征。 在本发明的一个方面，提供了一种集成电路，其具有MBIST电路，其被配置为串行测试集成电路的部件内的多个存储元件阵列，并且还对串行测试阵列进行并行初始化。 在本发明的另一方面，使用MBIST电路将阵列的存储元件设置为第一状态，然后在老化操作期间将其置于反向状态，以将两个相对状态中的每一个保持期望的时间，以便 要么强制集成电路部件的故障或者产生超过初级阶段的预应力部件。

公开(公告)号：US07506077B2

公开(公告)日：2009-03-17

申请号：US11158512

申请日：2005-06-22

申请人： Kay Hesse

发明人： Kay Hesse

IPC分类号： G06F3/00 ,  G06F13/20

CPC分类号： G06F13/385 ,  Y02D10/14 ,  Y02D10/151

摘要： A USB (Universal Serial Bus) OTG (On-The-Go) controller device and more generally a serial bus control circuit chip are provided which have improved port handler implementations. In one example, different port handler units may be provided which selectively support host and device functionality at the respective ports. In another example, a first port handler for providing host functionality and a second port handler for providing device functionality are provided which are of substantially the same hardware structure. In a further example, at least one port handler is provided that has a low level protocol module for handling packet assembly and/or disassembly, a transfer buffer module for buffering incoming or outgoing data to average out system memory latencies, and a memory access module for generating memory requests in compliance with host and/or device functionality.

摘要翻译： 提供USB（通用串行总线）OTG（On-The-Go）控制器设备，更一般地说，提供了具有改进的端口处理器实现的串行总线控制电路芯片。 在一个示例中，可以提供不同的端口处理器单元，其选择性地支持相应端口处的主机和设备功能。 在另一示例中，提供了用于提供主机功能的第一端口处理器和用于提供设备功能的第二端口处理器，其具有基本相同的硬件结构。 在另一示例中，提供至少一个端口处理器，其具有用于处理分组组合和/或反汇编的低级协议模块，用于缓冲输入或输出数据以平均化系统内存延迟的传输缓冲器模块，以及存储器访问模块 用于根据主机和/或设备功能生成内存请求。

公开(公告)号：US20120072789A1

公开(公告)日：2012-03-22

申请号：US12883450

申请日：2010-09-16

申请人： Wei-Yu Chen ,  Kevin Badgett ,  Kay Hesse

发明人： Wei-Yu Chen ,  Kevin Badgett ,  Kay Hesse

IPC分类号： G11C29/12 ,  G06F11/00

CPC分类号： G11C29/06 ,  G11C29/28 ,  G11C2029/2602

摘要： Integrated circuits with memory built-in self test (MBIST) circuitry and methods are disclosed that employ enhanced features. In one aspect of the invention, MBST circuitry is used set memory elements of arrays to a first state and then to an inverse state during a burn-in operation to maintain each of the two opposing states for a desired time in order to either force a failure of the integrated circuit component or produce a pre-stressed component beyond an infancy stage. Preferably, an integrated circuit is provided having MIBST circuitry configured to serially test multiple arrays of memory elements within a component of the integrated circuit and to also conduct parallel initialization of the serially tested arrays.

摘要翻译： 具有存储器内置自检（MBIST）电路和方法的集成电路被公开，其采用增强的特征。 在本发明的一个方面中，使用MBST电路将阵列的存储器元件设置为第一状态，然后在老化操作期间处于反向状态，以将两个相对状态中的每一个保持期望的时间，以便强制a 集成电路部件故障或产生超过初级阶段的预应力部件。 优选地，提供具有MIBST电路的集成电路，其被配置为串行测试集成电路的部件内的多个存储元件阵列，并且还对串行测试阵列进行并行初始化。

公开(公告)号：US20060095642A1

公开(公告)日：2006-05-04

申请号：US11230979

申请日：2005-09-20

申请人： Kay Hesse ,  Sven Mueller

发明人： Kay Hesse ,  Sven Mueller

IPC分类号： G06F13/20

CPC分类号： G06F13/385

摘要： A USB (Universal Serial Bus) controller technique for implementing OTG (On-The-Go) functionality is provided. The device may have an EHCI (Enhanced Host Controller Interface) compliant host control unit, and an OTG control unit to implement an OTG state machine partly in hardware and partly in software. The OTG control unit may have an OTG control register and an OTG status register which are accessible by software. Further, the USB controller device may have a device control unit to implement device functionality and a port multiplexer to assign a physical port to either the host or the device control unit. The OTG control unit may be comprised in the port multiplexer. Further, a software driver may read the OTG status register in response to receiving an interrupt from the USB controller device, and write to the OTG control register to force the USB controller device to change its OTG state.

摘要翻译： 提供了一种实现OTG（On-The-Go）功能的USB（通用串行总线）控制器技术。 该设备可以具有兼容EHCI（增强型主机控制器接口）的主机控制单元，以及OTG控制单元，部分以硬件部分实现OTG状态机部分软件。 OTG控制单元可以具有可由软件访问的OTG控制寄存器和OTG状态寄存器。 此外，USB控制器设备可以具有实现设备功能的设备控制单元和端口复用器以将物理端口分配给主机或设备控制单元。 OTG控制单元可以包括在端口复用器中。 此外，软件驱动程序可以响应于从USB控制器设备接收中断而读取OTG状态寄存器，并写入OTG控制寄存器以迫使USB控制器设备改变其OTG状态。

公开(公告)号：US08719481B2

公开(公告)日：2014-05-06

申请号：US13245899

申请日：2011-09-27

申请人： Kay Hesse

发明人： Kay Hesse

IPC分类号： G06F13/14 ,  G06F13/38

CPC分类号： G06F13/385 ,  G06F11/349

摘要： A circuit arrangement includes a plurality of functional units each of which comprises a plurality of data processing modules and a local controller. The plurality of data processing modules run a common system clock and are connected by a streaming data bus running a handshake-type streaming data transfer protocol. A profiling module of the circuit arrangement assesses control signals tapped at predefined interfaces of the streaming data bus during real time operation, for determining link performance and communication patterns for profiling and debugging purposes, and hence constitutes a simple and low cost approach for assessing intra-component and inter-component link performance and communication patterns on large SoCs. A method for profiling data flow for use in such a circuit arrangement is also provided.

摘要翻译： 电路装置包括多个功能单元，每个功能单元包括多个数据处理模块和本地控制器。 多个数据处理模块运行公共系统时钟，并通过运行握手型流数据传输协议的流数据总线进行连接。 电路装置的分析模块评估在实时操作期间在流数据总线的预定接口处被抽头的控制信号，用于确定用于分析和调试目的的链路性能和通信模式，并且因此构成用于评估帧内编码的简单和低成本的方法， 组件和组件间链路性能和大型SoC上的通信模式。 还提供了一种用于对这种电路装置使用的数据流进行分析的方法。

公开(公告)号：US08180947B2

公开(公告)日：2012-05-15

申请号：US11230979

申请日：2005-09-20

申请人： Kay Hesse ,  Sven Mueller

发明人： Kay Hesse ,  Sven Mueller

IPC分类号： G06F13/20

CPC分类号： G06F13/385

摘要： A USB (Universal Serial Bus) controller technique for implementing OTG (On-The-Go) functionality is provided. The device may have an EHCI (Enhanced Host Controller Interface) compliant host control unit, and an OTG control unit to implement an OTG state machine partly in hardware and partly in software. The OTG control unit may have an OTG control register and an OTG status register which are accessible by software. Further, the USB controller device may have a device control unit to implement device functionality and a port multiplexer to assign a physical port to either the host or the device control unit. The OTG control unit may be comprised in the port multiplexer. Further, a software driver may read the OTG status register in response to receiving an interrupt from the USB controller device, and write to the OTG control register to force the USB controller device to change its OTG state.

摘要翻译： 提供了一种用于实现OTG（On-The-Go）功能的USB（通用串行总线）控制器技术。 该设备可以具有兼容EHCI（增强型主机控制器接口）的主机控制单元，以及OTG控制单元，部分以硬件部分实现OTG状态机部分软件。 OTG控制单元可以具有可由软件访问的OTG控制寄存器和OTG状态寄存器。 此外，USB控制器设备可以具有实现设备功能的设备控制单元和端口复用器以将物理端口分配给主机或设备控制单元。 OTG控制单元可以包括在端口复用器中。 此外，软件驱动程序可以响应于从USB控制器设备接收中断而读取OTG状态寄存器，并写入OTG控制寄存器以迫使USB控制器设备改变其OTG状态。

公开(公告)号：US20100223511A1

公开(公告)日：2010-09-02

申请号：US12709565

申请日：2010-02-22

申请人： Markus Seuring ,  Kay Hesse ,  Kai Eichhorn

发明人： Markus Seuring ,  Kay Hesse ,  Kai Eichhorn

IPC分类号： G11C29/12 ,  G06F11/27

CPC分类号： G11C29/40 ,  G11C29/44

摘要： In a sophisticated semiconductor device including a large memory portion, a built-in self-test circuitry comprises a failure capturing logic that allows the capturing of a bitmap at a given instant in time without being limited to specific operating conditions in view of interfacing with external test equipment. Thus, although pipeline processing may be required due to the high speed operation during the self-test, reliable capturing of the bitmap may be achieved while maintaining high fault coverage of the test algorithm under consideration.

摘要翻译： 在包括大的存储器部分的复杂的半导体器件中，内置的自检电路包括故障捕获逻辑，其允许在给定时刻捕获位图，而不受限于特定的操作条件，与外部接口 测验设备。 因此，虽然由于在自检期间的高速操作可能需要流水线处理，但是可以在保持所考虑的测试算法的高故障覆盖的情况下实现位图的可靠捕获。

公开(公告)号：US08867680B2

公开(公告)日：2014-10-21

申请号：US13026505

申请日：2011-02-14

申请人： Lars Melzer ,  Kay Hesse

发明人： Lars Melzer ,  Kay Hesse

IPC分类号： H04L7/00 ,  G06F1/10 ,  G06F1/32

CPC分类号： G06F1/3203 ,  G06F1/10 ,  G06F1/3237 ,  Y02D10/128

摘要： A clock domain separation device and a method for operating the device is provided for separating two clock domains of a bus system in a system-on-chip (SoC). The clock domain separation device is a hardware module that acts as a guarding between the two clock domains that contain either bus end, and is generally applicable with handshake-type bus protocols. The clock domain separation module allows for each clock domain to switch its clock on and off independently from the state of the other clock domains, without risking data loss or protocol violation.

摘要翻译： 提供时钟域分离装置和用于操作该装置的方法，用于分离片上系统（SoC）中总线系统的两个时钟域。 时钟域分离设备是一个硬件模块，用作包含总线端的两个时钟域之间的保护，并且通常适用于握手型总线协议。 时钟域分离模块允许每个时钟域独立于其他时钟域的状态来切换其时钟的开启和关闭，而不会造成数据丢失或协议违规的风险。

公开(公告)号：US08458538B2

公开(公告)日：2013-06-04

申请号：US12709605

申请日：2010-02-22

申请人： Kay Hesse ,  Suresh Periyacheri

发明人： Kay Hesse ,  Suresh Periyacheri

IPC分类号： G11C29/00

CPC分类号： G11C29/38 ,  G11C29/02 ,  G11C29/023 ,  G11C29/12 ,  G11C29/50 ,  G11C29/50012

摘要： In a complex semiconductor device including embedded memories, the round trip latency may be determined during a memory self-test by applying a ping signal having the same latency as control and failure signals used during the self-test. The ping signal may be used for controlling an operation counter in order to obtain a reliable correspondence between the counter value and a memory operation causing a specified memory failure.

摘要翻译： 在包括嵌入式存储器的复杂半导体器件中，可以在存储器自检期间通过应用与在自检期间使用的控制和故障信号具有相同等待时间的ping信号来确定往返延迟。 ping信号可以用于控制操作计数器，以便获得计数器值与导致指定的存储器故障的存储器操作之间的可靠对应关系。