公开(公告)号：US20100223511A1

公开(公告)日：2010-09-02

申请号：US12709565

申请日：2010-02-22

Applicant: Markus Seuring ,  Kay Hesse ,  Kai Eichhorn

Inventor： Markus Seuring ,  Kay Hesse ,  Kai Eichhorn

IPC: G11C29/12 ,  G06F11/27

CPC classification number: G11C29/40 ,  G11C29/44

Abstract: In a sophisticated semiconductor device including a large memory portion, a built-in self-test circuitry comprises a failure capturing logic that allows the capturing of a bitmap at a given instant in time without being limited to specific operating conditions in view of interfacing with external test equipment. Thus, although pipeline processing may be required due to the high speed operation during the self-test, reliable capturing of the bitmap may be achieved while maintaining high fault coverage of the test algorithm under consideration.

Abstract translation: 在包括大的存储器部分的复杂的半导体器件中，内置的自检电路包括故障捕获逻辑，其允许在给定时刻捕获位图，而不受限于特定的操作条件，与外部接口 测验设备。 因此，虽然由于在自检期间的高速操作可能需要流水线处理，但是可以在保持所考虑的测试算法的高故障覆盖的情况下实现位图的可靠捕获。

公开(公告)号：US07502969B2

公开(公告)日：2009-03-10

申请号：US10858601

申请日：2004-06-01

Applicant: Douglas Richard Beard ,  Holger Eisenreich ,  Kai Eichhorn

Inventor： Douglas Richard Beard ,  Holger Eisenreich ,  Kai Eichhorn

IPC: G06F11/00

CPC classification number: G06F17/5022

Abstract: By providing at least two hardware representations of a specified circuit design, an efficient debugging system is provided that allows 100% design visibility at an extremely reduced simulation time owing to a time-shifted operation of the at least two hardware representations. Upon detection of a specified abort state in the leading hardware representation, the corresponding delayed state of the time-shifted hardware representation may be used for a subsequent simulation of only a relevant portion of the test run that has lead to the specified abort state.

Abstract translation: 通过提供指定电路设计的至少两个硬件表示，提供了一种有效的调试系统，其允许由于至少两个硬件表示的时移操作而极大地减少模拟时间的100％设计可视性。 在检测出领先的硬件表示中的指定的中止状态时，时移硬件表示的对应的延迟状态可以用于仅导致测试运行的相关部分的后续仿真，导致指定的中止状态。

公开(公告)号：US20060069969A1

公开(公告)日：2006-03-30

申请号：US11011397

申请日：2004-12-14

Applicant: Sebastian Ohnewald ,  Eric Swartzendruber ,  Kai Eichhorn

Inventor： Sebastian Ohnewald ,  Eric Swartzendruber ,  Kai Eichhorn

IPC: G01R31/28

CPC classification number: G01R31/2894 ,  G01R31/31707

Abstract: A device testing apparatus and method for testing a semiconductor device is provided. For device testing, stimulus data is generated and provided to the semiconductor device, and output data of the semiconductor device is then evaluated to verify proper operation of the semiconductor device. Further, data in the semiconductor device output data space is mapped to stimulus data, and a set of stimulus data is determined based on the mapping results for further testing.

Abstract translation: 提供一种用于测试半导体器件的器件测试装置和方法。 对于器件测试，产生刺激数据并提供给半导体器件，然后评估半导体器件的输出数据，以验证半导体器件的正常工作。 此外，半导体器件输出数据空间中的数据被映射到激励数据，并且基于用于进一步测试的映射结果确定一组激励数据。

公开(公告)号：US20050081113A1

公开(公告)日：2005-04-14

申请号：US10858601

申请日：2004-06-01

Applicant: Douglas Beard ,  Holger Eisenreich ,  Kai Eichhorn

Inventor： Douglas Beard ,  Holger Eisenreich ,  Kai Eichhorn

IPC: G06F11/00 ,  G06F17/50

CPC classification number: G06F17/5022

Abstract: By providing at least two hardware representations of a specified circuit design, an efficient debugging system is provided that allows 100% design visibility at an extremely reduced simulation time owing to a time-shifted operation of the at least two hardware representations. Upon detection of a specified abort state in the leading hardware representation, the corresponding delayed state of the time-shifted hardware representation may be used for a subsequent simulation of only a relevant portion of the test run that has lead to the specified abort state.

Abstract translation: 通过提供指定电路设计的至少两个硬件表示，提供了一种有效的调试系统，其允许由于至少两个硬件表示的时移操作而极大地减少模拟时间的100％设计可视性。 在检测出领先的硬件表示中的指定的中止状态时，时移硬件表示的对应的延迟状态可以用于仅导致测试运行的相关部分的后续仿真，导致指定的中止状态。

公开(公告)号：US08307249B2

公开(公告)日：2012-11-06

申请号：US12709565

申请日：2010-02-22

Applicant: Markus Seuring ,  Kay Hesse ,  Kai Eichhorn

Inventor： Markus Seuring ,  Kay Hesse ,  Kai Eichhorn

IPC: G11C29/00

CPC classification number: G11C29/40 ,  G11C29/44

Abstract: In a sophisticated semiconductor device including a large memory portion, a built-in self-test circuitry comprises a failure capturing logic that allows the capturing of a bitmap at a given instant in time without being limited to specific operating conditions in view of interfacing with external test equipment. Thus, although pipeline processing may be required due to the high speed operation during the self-test, reliable capturing of the bitmap may be achieved while maintaining high fault coverage of the test algorithm under consideration.

Abstract translation: 在包括大的存储器部分的复杂的半导体器件中，内置的自检电路包括故障捕获逻辑，其允许在给定时刻捕获位图，而不受限于特定的操作条件，与外部接口 测验设备。 因此，虽然由于在自检期间的高速操作可能需要流水线处理，但是可以在保持所考虑的测试算法的高故障覆盖的情况下实现位图的可靠捕获。