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    Method for performing a test case with a LBIST engine on an integrated circuit, integrated circuit and method for specifying an integrated circuit
    2.
    发明授权
    Method for performing a test case with a LBIST engine on an integrated circuit, integrated circuit and method for specifying an integrated circuit 失效
    在集成电路上使用LBIST引擎执行测试用例的方法，用于指定集成电路的集成电路和方法

    公开(公告)号：US07877655B2

    公开(公告)日：2011-01-25

    申请号：US11855505

    申请日：2007-09-14

    申请人： Thuyen Le ,  Thomas Pflueger ,  Martin Padeffke ,  Stefan Bonsels

    发明人： Thuyen Le ,  Thomas Pflueger ,  Martin Padeffke ,  Stefan Bonsels

    IPC分类号： G01R31/28

    CPC分类号： G01R31/3187 ,  G01R31/318502

    摘要： A method for performing a test case with at least one LBIST engine on an integrated circuit with a plurality of storage elements and logic circuits interconnected according to a predetermined scheme. The LBIST engine is partially built up by storage elements and/or logic circuits. At least one scan chain is formed as a series of selected storage elements and the other storage elements are used for the LBIST engine or a part of said LBIST engine in a testing mode. The scan chain is driven by a test pattern and the LBIST test case is testing those parts of the logic circuits corresponding to the storage elements of said scan chain.

    摘要翻译： 一种在具有根据预定方案互连的多个存储元件和逻辑电路的集成电路上的至少一个LBIST引擎执行测试用例的方法。 LBIST引擎部分由存储元件和/或逻辑电路构成。 至少一个扫描链形成为一系列所选择的存储元件，并且其它存储元件用于LBIST引擎或在测试模式中用于所述LBIST引擎的一部分。 扫描链由测试模式驱动，LBIST测试用例正在测试对应于所述扫描链的存储元件的逻辑电路的那些部分。

    System for performing a serial communication between a central control block and satellite components
    3.
    发明授权
    System for performing a serial communication between a central control block and satellite components 有权
    用于执行中央控制块和卫星组件之间的串行通信的系统

    公开(公告)号：US07788432B2

    公开(公告)日：2010-08-31

    申请号：US12244430

    申请日：2008-10-02

    申请人： Ralf Ludewig ,  Thuyen Le ,  Tobias Webel ,  Klaus Peter Gungl

    发明人： Ralf Ludewig ,  Thuyen Le ,  Tobias Webel ,  Klaus Peter Gungl

    IPC分类号： G06F13/00

    CPC分类号： G06F13/4286

    摘要： The various embodiments described herein relate to a system for performing a serial communication between a central control block and a plurality of satellite components within a semiconductor chip. The system comprises at least one logical ring that serially connects the satellite components to the central control block. The system further comprises a centralized timer. The satellite components aid the system in obeying protocols and performing direct accesses to and/or from registers. The logical ring comprises at least one data channel that is provided for transmitting data packets and address packets. Single-envelope transactions are implemented. Errors of the satellite components associated with the single-envelope transactions are reported to the central control block as additional acknowledgement information.

    摘要翻译： 这里描述的各种实施例涉及用于在中央控制块和半导体芯片内的多个卫星部件之间执行串行通信的系统。 该系统包括将卫星组件串行连接到中央控制块的至少一个逻辑环。 该系统还包括集中式定时器。 卫星组件帮助系统服从协议并执行对寄存器的访问和/或从寄存器的直接访问。 逻辑环包括提供用于发送数据分组和地址分组的至少一个数据信道。 实施单包络交易。 与单包络事务相关联的卫星组件的错误作为附加确认信息报告给中央控制块。

    METHOD FOR PERFORMING LOGIC BUILT-IN-SELF-TEST CYCLES ON A SEMICONDUCTOR CHIP AND A CORRESPONDING SEMICONDUCTOR CHIP WITH A TEST ENGINE
    4.
    发明申请
    METHOD FOR PERFORMING LOGIC BUILT-IN-SELF-TEST CYCLES ON A SEMICONDUCTOR CHIP AND A CORRESPONDING SEMICONDUCTOR CHIP WITH A TEST ENGINE 审中-公开
    用于在半导体芯片上执行逻辑内置自测试循环的方法和与测试引擎相关的半导体芯片

    公开(公告)号：US20090228751A1

    公开(公告)日：2009-09-10

    申请号：US12125476

    申请日：2008-05-22

    申请人： Tilman Gloekler ,  Christoph Jaeschke ,  Thuyen Le ,  Martin Padeffke

    发明人： Tilman Gloekler ,  Christoph Jaeschke ,  Thuyen Le ,  Martin Padeffke

    IPC分类号： G01R31/3177 ,  G06F11/25

    CPC分类号： G01R31/318536 ,  G01R31/318547

    摘要： A method, structure and design system for performing logic built-in-self-test (LBIST) cycles on a semiconductor chip with a plurality of logic circuits and a plurality of storage elements connected serially to a number of LBIST stumps (pattern segments) between a pseudo-random-pattern generator (30) and a multiple-input-signature register. The semiconductor chip is subdivided into partitions, such that LBIST cycles may be run separately or in parallel for one or more partitions. The LBIST cycles may also be run separately or in parallel inter-connections between the partitions. The partitions to be tested are controlled by at least one corresponding clock signal, and the inter-connections to be tested are controlled by at least one corresponding clock signal.

    摘要翻译： 一种用于在半导体芯片上执行逻辑内置自检（LBIST）周期的方法，结构和设计系统，其具有多个逻辑电路和多个存储元件，所述多个逻辑电路和多个存储元件串联连接到多个LBIST树桩（图案段）之间， 伪随机模式生成器（30）和多输入签名寄存器。 半导体芯片被细分为分区，使得LBIST周期可以针对一个或多个分区单独运行或并行运行。 LBIST循环也可以分开运行或在分区之间并行连接。 要测试的分区由至少一个对应的时钟信号控制，并且待测试的互连由至少一个相应的时钟信号控制。

    System for performing a serial communication between a central control block and satellite components
    5.
    发明申请
    System for performing a serial communication between a central control block and satellite components 有权
    用于执行中央控制块和卫星组件之间的串行通信的系统

    公开(公告)号：US20090113094A1

    公开(公告)日：2009-04-30

    申请号：US12244430

    申请日：2008-10-02

    申请人： Ralf Ludewig ,  Thuyen Le ,  Tobias Webel ,  Klaus Peter Gungl

    发明人： Ralf Ludewig ,  Thuyen Le ,  Tobias Webel ,  Klaus Peter Gungl

    IPC分类号： G06F13/00

    CPC分类号： G06F13/4286

    摘要： The various embodiments described herein relate to a system for performing a serial communication between a central control block and a plurality of satellite components within a semiconductor chip. The system comprises at least one logical ring that serially connects the satellite components to the central control block. The system further comprises a centralized timer. The satellite components aid the system in obeying protocols and performing direct accesses to and/or from registers. The logical ring comprises at least one data channel that is provided for transmitting data packets and address packets. Single-envelope transactions are implemented. Errors of the satellite components associated with the single-envelope transactions are reported to the central control block as additional acknowledgement information.

    摘要翻译： 这里描述的各种实施例涉及用于在中央控制块和半导体芯片内的多个卫星部件之间进行串行通信的系统。 该系统包括将卫星组件串行连接到中央控制块的至少一个逻辑环。 该系统还包括集中式定时器。 卫星组件帮助系统服从协议并执行对寄存器的访问和/或从寄存器的直接访问。 逻辑环包括提供用于发送数据分组和地址分组的至少一个数据信道。 实施单包络交易。 与单包络事务相关联的卫星组件的错误作为附加确认信息报告给中央控制块。

    Hardware structure for a transmission/reception device for mobile radio applications, and method for processing data in such a transmission/reception device
    6.
    发明授权
    Hardware structure for a transmission/reception device for mobile radio applications, and method for processing data in such a transmission/reception device 有权
    用于移动无线电应用的发送/接收装置的硬件结构，以及用于处理这种发送/接收装置中的数据的方法

    公开(公告)号：US07050826B2

    公开(公告)日：2006-05-23

    申请号：US10832675

    申请日：2004-04-27

    申请人： Burkhard Becker ,  Thuyen Le

    发明人： Burkhard Becker ,  Thuyen Le

    IPC分类号： H04M1/00 ,  G06F15/00

    CPC分类号： H04B1/7117 ,  H04B1/0003 ,  H04B1/406 ,  H04B1/7113 ,  H04B2201/7071

    摘要： A transmission/reception device for mobile radio applications has a microprocessor (DSP), at least one task-specific processor (P1, P2, P3) and a processor interface (2). The task-specific processor (P1, P2, P3) can be configured, by transmitting suitable configuration instructions from the microprocessor via the processor interface (2), such that a basic function performed by the task-specific processor (P1, P2, P3) can be controlled by changing configuration parameters.

    摘要翻译： 用于移动无线电应用的发送/接收装置具有微处理器（DSP），至少一个任务专用处理器（P 1，P 2，P 3）和处理器接口（2）。 可以通过经由处理器接口（2）从微处理器发送合适的配置指令来配置任务特定处理器（P 1，P 2，P 3），使得由任务专用处理器（P 1 ，P 2，P 3）可以通过改变配置参数来控制。

    Method for switching between two redundant oscillator signals within an alignment element
    7.
    发明授权
    Method for switching between two redundant oscillator signals within an alignment element 有权
    用于在对准元件内切换两个冗余振荡器信号的方法

    公开(公告)号：US08055931B2

    公开(公告)日：2011-11-08

    申请号：US12246123

    申请日：2008-10-06

    申请人： Ralf Ludewig ,  Thuyen Le ,  Tilman Gloekler ,  Willm Hinrichs

    发明人： Ralf Ludewig ,  Thuyen Le ,  Tilman Gloekler ,  Willm Hinrichs

    IPC分类号： G06F1/04

    CPC分类号： G06F1/12

    摘要： A method is provided for switching between two oscillator signals within an alignment element. In accordance with the method, one of the two oscillator signals one is selected as a first master signal in order to provide an output stepping signal at an output of the alignment element. The method comprises introducing a virtual stepping signal when a switch between the two oscillator signals occurs or when a failure in the first master signal is detected. The method further comprises sending the virtual stepping signal to the output of the alignment element in the event of a switch until an alignment with a new master signal is completed.

    摘要翻译： 提供了一种用于在对准元件内的两个振荡器信号之间切换的方法。 根据该方法，选择两个振荡器信号之一作为第一主信号，以便在对准元件的输出处提供输出步进信号。 该方法包括当两个振荡器信号之间的开关发生时或当检测到第一主信号的故障时引入虚拟步进信号。 该方法还包括在开关的情况下将虚拟步进信号发送到对准元件的输出，直到与新的主信号的对准完成。

    Accounting for Microprocessor Resource Consumption
    9.
    发明申请
    Accounting for Microprocessor Resource Consumption 失效
    计算微处理器资源消耗

    公开(公告)号：US20080209245A1

    公开(公告)日：2008-08-28

    申请号：US12029636

    申请日：2008-02-12

    申请人： Daniel Becker ,  Rafael Keggenhoff ,  Thuyen Le ,  Tobias Webel ,  Matthias Woehrle

    发明人： Daniel Becker ,  Rafael Keggenhoff ,  Thuyen Le ,  Tobias Webel ,  Matthias Woehrle

    IPC分类号： G06F1/06 ,  G06F1/32

    CPC分类号： G06F11/3058 ,  G06F11/3024 ,  G06F11/3419 ,  G06F11/348

    摘要： Techniques for accounting microprocessor resource consumption. The present invention provides an automatic method to timely determine the current microprocessor clock frequency. Information provided by timer facilities of the microprocessor is reused by sampling this information at constant intervals. Such direct derivation of the microprocessor clock frequency is a real-time method that also takes into consideration secondary effects. Examples for such secondary effects include clock frequency variations across chips due to manufacturing variations, any degradation due to performance loss by thermal, or other detrimental effects as well as any voltage changes. In the preferred embodiment of the invention, the real-time microprocessor clock frequency determination is implemented as part of the microprocessor itself. No additional service processors or other external hardware facilities are needed in order to control the microprocessor clock frequency determination function.

    摘要翻译： 用于会计微处理器资源消耗的技术。 本发明提供了一种能够及时确定当前微处理器时钟频率的自动方法。 由微处理器的定时器设备提供的信息通过以恒定的间隔对该信息进行采样来重用。 微处理器时钟频率的这种直接推导是一种也考虑到二次效应的实时方法。 这种二次效应的示例包括由于制造变化导致的芯片之间的时钟频率变化，由于热损耗导致的任何劣化或其他有害影响以及任何电压变化。 在本发明的优选实施例中，实时微处理器时钟频率确定被实现为微处理器本身的一部分。 为了控制微处理器的时钟频率确定功能，不需要附加的服务处理器或其他外部硬件设备。