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公开(公告)号：US20230145380A1
公开(公告)日：2023-05-11
申请号：US18053222
申请日：2022-11-07
Applicant: KOREA ELECTRONICS TECHNOLOGY INSTITUTE
Inventor： Jong Min YOOK , Je In YU , Dong Su KIM
IPC: H01P3/12 , H01L23/498 , H01L23/043 , H01L21/48 , H01P11/00
CPC classification number: H01P3/121 , H01L23/49827 , H01L23/043 , H01L21/486 , H01P11/002
Abstract: A waveguide package and a method for manufacturing the same are disclosed. The waveguide package includes a package structure including a waveguide opened toward one side surface of a substrate, a semiconductor chip mounted on one surface of the package structure and configured to output an electrical signal to the waveguide. Since an interior of the waveguide is filled with air, electrical loss of the waveguide is minimized The cavity is formed by processing the substrate made of photosensitive glass. Accordingly, the waveguide may be accurately formed. An electronic circuit may also be formed at the waveguide package. Accordingly, it may be possible to provide a waveguide package enhanced in degree of integration.
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公开(公告)号：US20160056108A1
公开(公告)日：2016-02-25
申请号：US14781991
申请日：2014-04-24
Applicant: KOREA ELECTRONICS TECHNOLOGY INSTITUTE
Inventor： Jun Chul KIM , Dong Su KIM , Se Hoon PARK , Jong Min YOOK
IPC: H01L23/522 , H01L23/532 , H01L21/768 , H01L23/528
CPC classification number: H01L23/5226 , H01L21/76805 , H01L21/76843 , H01L21/76898 , H01L23/481 , H01L23/5222 , H01L23/5225 , H01L23/5227 , H01L23/5228 , H01L23/528 , H01L23/5329 , H01L28/10 , H01L2924/0002 , H01L2924/00
Abstract: A method for forming a wiring for a semiconductor device according to an aspect of the present invention includes: forming a predetermined pattern on a first surface of a silicon substrate by selectively etching the first surface; coating, with a metal layer, a selected area of the first surface, including an area whereat the predetermined pattern is formed; forming organic material in the first surface to fill an etched portion and cover the coated metal layer; forming a plurality of via holes in the organic material and connecting the metal wiring to the coated metal layer through the via holes; and grinding a second surface corresponding to the first surface to remove a part of the metal layer formed in the etched portion.
Abstract translation: 根据本发明的一个方面的用于形成用于半导体器件的布线的方法包括：通过选择性地蚀刻第一表面在硅衬底的第一表面上形成预定图案; 用金属层涂覆第一表面的选定区域，包括形成预定图案的区域; 在第一表面中形成有机材料以填充蚀刻部分并覆盖涂覆的金属层; 在所述有机材料中形成多个通孔，并且通过所述通孔将所述金属布线连接到所述涂覆的金属层; 并研磨对应于第一表面的第二表面以去除在蚀刻部分中形成的金属层的一部分。
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公开(公告)号：US20190198413A1
公开(公告)日：2019-06-27
申请号：US16225238
申请日：2018-12-19
Applicant: KOREA ELECTRONICS TECHNOLOGY INSTITUTE
Inventor： Jong Min YOOK , Jun Chul KIM , Dong Su KIM
IPC: H01L23/31 , H01L23/522 , H01L23/528 , H01L21/56 , H01L23/00
CPC classification number: H01L23/3128 , H01L21/565 , H01L23/5226 , H01L23/5283 , H01L24/09 , H01L24/17 , H01L2224/0231 , H01L2224/02381
Abstract: The present invention provides a semiconductor package and a manufacturing method thereof, the semiconductor package including: at least one semiconductor chip; a molding layer surrounding the semiconductor chip; a redistribution layer provided on a first surface of the molding layer to transmit an electrical signal; and at least one connecting element transmitting an electrical signal from the first surface of the molding layer to a second surface of the molding layer. According to the present invention, since the connecting element, which is an independent element capable of transmitting an electrical signal in a vertical direction of the semiconductor package, is included in the molding layer, it is possible to integrate an electric element such as an antenna into a rear surface space of the semiconductor package.
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公开(公告)号：US20160181242A1
公开(公告)日：2016-06-23
申请号：US14960501
申请日：2015-12-07
Applicant: Korea Electronics Technology Institute
Inventor： Jong Min YOOK , Jun Chul KIM , Dong Su KIM , Se Hoon PARK , Jong In RYU , Jong Chul PARK
CPC classification number: H01L28/60 , H01L27/016 , H01L28/10
Abstract: The present invention relates to a passive device and manufacturing method thereof. A capacitor according to the present invention includes: a capacitor thin film pattern formed on the upper surface of a substrate; a plurality of trenches formed by etching the substrate formed with the capacitor thin film pattern which defines the unit area of the capacitor; an insulation layer, which fills the trench, formed with capacitor interconnection holes for exposing the metal layers formed in the substrate and constituting the capacitor; and a plurality of capacitor electrode interconnection wires formed by filling the capacitor interconnection holes with a conductive material, wherein the lower surface of the substrate is being polished in a way that the insulation layer formed in the trenches is exposed.
Abstract translation: 无源器件及其制造方法技术领域本发明涉及无源器件及其制造方法。 根据本发明的电容器包括：形成在基板的上表面上的电容器薄膜图案; 通过蚀刻形成有限定电容器的单位面积的电容器薄膜图案的基板形成的多个沟槽; 绝缘层，其填充沟槽，形成有用于暴露形成在衬底中并构成电容器的金属层的电容器互连孔; 以及通过用导电材料填充电容器互连孔而形成的多个电容器电极互连线，其中衬底的下表面被抛光，使得形成在沟槽中的绝缘层被暴露。
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公开(公告)号：US20220328253A1
公开(公告)日：2022-10-13
申请号：US17709338
申请日：2022-03-30
Applicant: KOREA ELECTRONICS TECHNOLOGY INSTITUTE
Inventor： Jong Min YOOK , Je In YU , Jun Chul KIM , Dong Su KIM
Abstract: The present invention provides a method for manufacturing a high frequency capacitor, including preparing a substrate for formation of the capacitor, forming a dielectric layer at an upper surface of the substrate, forming an upper electrode at an upper surface of the dielectric layer, and removing a portion of a lower surface of the substrate, to expose a lower surface of the dielectric layer, and forming a lower electrode at the lower surface of the dielectric layer. The high frequency capacitor includes a dielectric layer having a uniform surface, a thick upper electrode, and a thick lower electrode and, as such, exhibits high quality factor (Q) even at a high frequency.
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Patent Agency Ranking
6.发明申请公开(公告)号：US20200381797A1
公开(公告)日：2020-12-03
申请号：US15930404
申请日：2020-05-12
Applicant: KOREA ELECTRONICS TECHNOLOGY INSTITUTE
Inventor： Jong Min YOOK , Jun Chul KIM , Dong Su KIM
Abstract: A quasi-coaxial transmission line, a semiconductor package including the same and a method of manufacturing the same are disclosed. The quasi-coaxial transmission line includes a core, which is formed through an upper surface and a lower surface of a base substrate so as to transmit an electrical signal, and a shield, which is spaced apart from the core and which coaxially surrounds a side surface of the core, at least a portion of the shield being removed so as to form an open portion. The quasi-coaxial transmission line is capable of preventing distortion of an electrical signal at a portion thereof that is connected to an external circuit board and to reduce an area of a semiconductor package including the quasi-coaxial transmission line.
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7.发明申请公开(公告)号：US20200373256A1
公开(公告)日：2020-11-26
申请号：US16878727
申请日：2020-05-20
Applicant: Korea Electronics Technology Institute
Inventor： Jong Min YOOK , Jun Chul KIM , Dong Su KIM
Abstract: A semiconductor package includes a semiconductor chip including an electrode pad formed on the top surface thereof, a passive device embedded in the semiconductor package, the passive device having no functional electrode on the top surface thereof, a cover layer covering the semiconductor chip and the passive device, and at least one electrode pattern formed on the cover layer to transmit electrical signals. The cover layer includes at least one first opening formed to expose a region in which the functional electrode is to be formed. The electrode pattern includes a functional electrode portion formed in a region in which the functional electrode of the passive device is to be formed through the first opening. In the process of forming the electrode pattern, a functional electrode of the passive device is formed together therewith, thereby eliminating a separate step of manufacturing a functional electrode and thus reducing manufacturing costs.
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8.发明公开公开(公告)号：US20240282724A1
公开(公告)日：2024-08-22
申请号：US18439938
申请日：2024-02-13
Applicant: KOREA ELECTRONICS TECHNOLOGY INSTITUTE
Inventor： Jong Min YOOK , Je In YU , Dong Su KIM
IPC: H01L23/66 , H01L23/00 , H01L23/367 , H01L23/498
CPC classification number: H01L23/66 , H01L23/367 , H01L23/49827 , H01L24/32 , H01L2223/6677 , H01L2224/32225 , H01L2924/181
Abstract: An antenna-integrated high-frequency semiconductor package, including a substrate including a recess concave on a first surface and a first through-hole penetrating from the first surface to a second surface, a ground layer configured to cover the first surface of the substrate and the recess, a semiconductor chip mounted on the ground layer of the recess, an insulating layer configured to entirely cover the substrate, the ground layer, and the semiconductor chip, and a conductive layer formed on the insulating layer, the conductive layer including an electrode pattern connected to the semiconductor chip, an antenna formed on a second surface of the insulating layer, and a signal via configured to transmit an electrical signal between the electrode pattern and the antenna through a second through-hole formed in the first through-hole to penetrate from the first surface to the second surface of the insulating layer.
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9.发明申请公开(公告)号：US20200091028A1
公开(公告)日：2020-03-19
申请号：US16184191
申请日：2018-11-08
Applicant: KOREA ELECTRONICS TECHNOLOGY INSTITUTE
Inventor： Jong Min YOOK , Jun Chul KIM , Dong Su KIM
IPC: H01L23/367 , H01L23/00 , H01L23/66 , H01L23/498 , H01L23/532
Abstract: Disclosed is a semiconductor package. The semiconductor package includes a semiconductor chip on which an electrode pad is disposed, at least one input/output segment disposed around a side surface of the semiconductor chip to be spaced apart from the semiconductor chip and transmitting an electric signal, and an insulating layer filled between the semiconductor chip and the input/output segment. The insulating layer is provided on the semiconductor chip and the input/output segment to fix and insulate the semiconductor chip and the input/output segment from each other. The semiconductor further includes an electrode pattern provided on the insulating layer and configured to electrically connect the electrode pad of the semiconductor chip and the input/output segment.
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公开(公告)号：US20170309541A1
公开(公告)日：2017-10-26
申请号：US15441188
申请日：2017-02-23
Applicant: KOREA ELECTRONICS TECHNOLOGY INSTITUTE
Inventor： Jun Chul KIM , Dong Su KIM , Jong Min YOOK
IPC: H01L23/367 , H01L23/373 , H01L23/14 , H01L21/52 , H01L23/13 , H01L21/56 , H01L23/485
CPC classification number: H01L23/3675 , H01L21/52 , H01L21/56 , H01L21/568 , H01L23/13 , H01L23/142 , H01L23/367 , H01L23/3735 , H01L23/3736 , H01L23/485 , H01L23/5389 , H01L2224/04105 , H01L2224/19
Abstract: Disclosed is a semiconductor package including: a base substrate provided with at least one cavity and made of a metallic material; at least one semiconductor chip mounted in the cavity; and a heat dissipating member arranged in a gap between an inner surface of the cavity and the semiconductor chip.
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