公开(公告)号：US20160181242A1

公开(公告)日：2016-06-23

申请号：US14960501

申请日：2015-12-07

Applicant: Korea Electronics Technology Institute

Inventor： Jong Min YOOK ,  Jun Chul KIM ,  Dong Su KIM ,  Se Hoon PARK ,  Jong In RYU ,  Jong Chul PARK

IPC: H01L27/07 ,  H01L49/02

CPC classification number: H01L28/60 ,  H01L27/016 ,  H01L28/10

Abstract: The present invention relates to a passive device and manufacturing method thereof. A capacitor according to the present invention includes: a capacitor thin film pattern formed on the upper surface of a substrate; a plurality of trenches formed by etching the substrate formed with the capacitor thin film pattern which defines the unit area of the capacitor; an insulation layer, which fills the trench, formed with capacitor interconnection holes for exposing the metal layers formed in the substrate and constituting the capacitor; and a plurality of capacitor electrode interconnection wires formed by filling the capacitor interconnection holes with a conductive material, wherein the lower surface of the substrate is being polished in a way that the insulation layer formed in the trenches is exposed.

Abstract translation: 无源器件及其制造方法技术领域本发明涉及无源器件及其制造方法。 根据本发明的电容器包括：形成在基板的上表面上的电容器薄膜图案; 通过蚀刻形成有限定电容器的单位面积的电容器薄膜图案的基板形成的多个沟槽; 绝缘层，其填充沟槽，形成有用于暴露形成在衬底中并构成电容器的金属层的电容器互连孔; 以及通过用导电材料填充电容器互连孔而形成的多个电容器电极互连线，其中衬底的下表面被抛光，使得形成在沟槽中的绝缘层被暴露。

公开(公告)号：US20160056108A1

公开(公告)日：2016-02-25

申请号：US14781991

申请日：2014-04-24

Applicant: KOREA ELECTRONICS TECHNOLOGY INSTITUTE

Inventor： Jun Chul KIM ,  Dong Su KIM ,  Se Hoon PARK ,  Jong Min YOOK

IPC: H01L23/522 ,  H01L23/532 ,  H01L21/768 ,  H01L23/528

CPC classification number: H01L23/5226 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5222 ,  H01L23/5225 ,  H01L23/5227 ,  H01L23/5228 ,  H01L23/528 ,  H01L23/5329 ,  H01L28/10 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming a wiring for a semiconductor device according to an aspect of the present invention includes: forming a predetermined pattern on a first surface of a silicon substrate by selectively etching the first surface; coating, with a metal layer, a selected area of the first surface, including an area whereat the predetermined pattern is formed; forming organic material in the first surface to fill an etched portion and cover the coated metal layer; forming a plurality of via holes in the organic material and connecting the metal wiring to the coated metal layer through the via holes; and grinding a second surface corresponding to the first surface to remove a part of the metal layer formed in the etched portion.

Abstract translation: 根据本发明的一个方面的用于形成用于半导体器件的布线的方法包括：通过选择性地蚀刻第一表面在硅衬底的第一表面上形成预定图案; 用金属层涂覆第一表面的选定区域，包括形成预定图案的区域; 在第一表面中形成有机材料以填充蚀刻部分并覆盖涂覆的金属层; 在所述有机材料中形成多个通孔，并且通过所述通孔将所述金属布线连接到所述涂覆的金属层; 并研磨对应于第一表面的第二表面以去除在蚀刻部分中形成的金属层的一部分。