SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

    公开(公告)号:US20210005744A1

    公开(公告)日:2021-01-07

    申请号:US17025213

    申请日:2020-09-18

    申请人: DENSO CORPORATION

    摘要: A semiconductor device includes: an inversion type semiconductor element that includes: a substrate having a first conductivity type or a second conductivity type; a first conductivity type layer formed on the substrate; a second conductivity type region that is formed on the first conductivity type layer; a JFET portion that is formed on the first conductivity type layer, is sandwiched by the second conductivity type region to be placed; a source region that is formed on the second conductivity region; a gate insulation film formed on a channel region that is a part of the second conductivity type region; a gate electrode formed on the gate insulation film; an interlayer insulation film covering the gate electrode and the gate insulation film, and including a contact hole; a source electrode electrically connected to the source region through the contact hole; and a drain electrode formed on a back side of the substrate.

    SILICON CARBIDE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR

    公开(公告)号:US20190386095A1

    公开(公告)日:2019-12-19

    申请号:US16304866

    申请日:2017-06-29

    摘要: Intervals of the frame portion and the p type guard ring on a cell portion side are made narrower than other parts, and the narrowed part provides a dot line portion. By narrowing the intervals of the frame portion and the p type guard ring on the cell portion side, the electric field concentration is reduced on the cell portion side, and the equipotential line directs to more outer circumferential side. By providing the dot line portions, the difference in the formation areas of the trench per unit area in the cell portion, the connection portion and the guard ring portion is reduced, and the thicknesses of the p type layers formed on the cell portion, the connection portion and the guard ring portion are uniformed. Thereby, when etching-back the p type layer, the p type layer is prevented from remaining as a residue in the guard ring portion.

    COMPOUND SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

    公开(公告)号:US20190035882A1

    公开(公告)日:2019-01-31

    申请号:US16069914

    申请日:2017-01-19

    申请人: DENSO CORPORATION

    摘要: A method for manufacturing a compound semiconductor device includes: providing a semiconductor substrate including a foundation layer having a first conductivity type; forming a deep trench in the foundation layer; and forming a deep layer having a second conductivity type by introducing material gas of the compound semiconductor while introducing dopant gas into an epitaxial growth equipment to cause epitaxial growth of the deep layer in the deep trench. A period in which a temperature in the epitaxial growth equipment is increased to a temperature of the epitaxial growth of the deep layer is defined as a temperature increasing period. In the forming the deep layer, the deep layer is further formed in a bottom corner portion of the deep trench by starting the introducing of the dopant gas during the temperature increasing period and starting the introducing of the material gas after the temperature increasing period.

    SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME

    公开(公告)号:US20190288107A1

    公开(公告)日:2019-09-19

    申请号:US16421849

    申请日:2019-05-24

    摘要: A silicon carbide semiconductor device includes: a substrate; a drift layer over the substrate; a base region over the drift layer; multiple source regions over an upper layer portion of the base region; a contact region over the upper layer portion of the base region between opposing source regions; multiple trenches from a surface of each source region to a depth deeper than the base region; a gate electrode on a gate insulating film in each trench; a source electrode electrically connected to the source regions and the contact region; a drain electrode over a rear surface of the substrate; and multiple electric field relaxation layers in the drift layer between adjacent trenches. Each electric field relaxation layer includes: a first region at a position deeper than the trenches; and a second region from a surface of the drift layer to the first region.