公开(公告)号：US20170012108A1

公开(公告)日：2017-01-12

申请号：US15113475

申请日：2015-01-14

申请人： DENSO CORPORATION ,  TOYOTA JIDOSHA KABUSHIKI KAISHA

发明人： Jun SAKAKIBARA ,  Nozomu AKAGI ,  Shoji MIZUNO ,  Yuichi TAKEUCHI ,  Katsumi SUZUKI

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L21/02 ,  H01L23/544 ,  H01L29/16 ,  H01L29/10

CPC分类号： H01L29/66068 ,  H01L21/02378 ,  H01L21/0243 ,  H01L21/02529 ,  H01L21/0262 ,  H01L21/02634 ,  H01L21/0465 ,  H01L21/0475 ,  H01L21/0485 ,  H01L21/049 ,  H01L21/2015 ,  H01L21/2033 ,  H01L21/266 ,  H01L21/3065 ,  H01L21/3083 ,  H01L23/544 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/0886 ,  H01L29/1037 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/401 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/66484 ,  H01L29/66666 ,  H01L29/66734 ,  H01L29/7396 ,  H01L29/7397 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7831 ,  H01L2223/54426 ,  H01L2223/5446 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a method for manufacturing a semiconductor device, when a second conductive type impurity layer is formed to provide a deep layer having a second conductive type in a first concavity and to provide a channel layer having the second conductive type on a surface of a drift layer, an epitaxial growth is performed under a growth condition that a contact trench provided by a recess is formed on a surface of a part of the second conductive type impurity layer corresponding to a center position of the first concavity, and a contact region is formed by ion-implanting a second conductive type impurity on a bottom of the contact trench.

摘要翻译： 在制造半导体器件的方法中，当形成第二导电型杂质层以在第一凹部中提供具有第二导电类型的深层并且在漂移层的表面上提供具有第二导电类型的沟道层 在与第一凹部的中心位置对应的第二导电型杂质层的一部分的表面上形成由凹部设置的接触沟槽的生长条件进行外延生长，并且接触区域由 在接触沟槽的底部离子注入第二导电型杂质。

公开(公告)号：US20190288107A1

公开(公告)日：2019-09-19

申请号：US16421849

申请日：2019-05-24

申请人： DENSO CORPORATION ,  TOYOTA JIDOSHA KABUSHIKI KAISHA

发明人： Hirotaka SAIKAKU ,  Jun SAKAKIBARA ,  Shoji MIZUNO ,  Yuichi TAKEUCHI

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/10 ,  H01L29/08 ,  H01L29/16

摘要： A silicon carbide semiconductor device includes: a substrate; a drift layer over the substrate; a base region over the drift layer; multiple source regions over an upper layer portion of the base region; a contact region over the upper layer portion of the base region between opposing source regions; multiple trenches from a surface of each source region to a depth deeper than the base region; a gate electrode on a gate insulating film in each trench; a source electrode electrically connected to the source regions and the contact region; a drain electrode over a rear surface of the substrate; and multiple electric field relaxation layers in the drift layer between adjacent trenches. Each electric field relaxation layer includes: a first region at a position deeper than the trenches; and a second region from a surface of the drift layer to the first region.

公开(公告)号：US20170263757A1

公开(公告)日：2017-09-14

申请号：US15505267

申请日：2015-09-08

申请人： DENSO CORPORATION ,  TOYOTA JIDOSHA KABUSHIKI KAISHA

发明人： Hirotaka SAIKAKU ,  Jun SAKAKIBARA ,  Shoji MIZUNO ,  Yuichi TAKEUCHI

IPC分类号： H01L29/78 ,  H01L21/04 ,  H01L29/10 ,  H01L29/66 ,  H01L29/06 ,  H01L29/16

CPC分类号： H01L29/7813 ,  H01L21/046 ,  H01L21/047 ,  H01L29/0688 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/66068

摘要： A silicon carbide semiconductor device includes: a substrate; a drift layer over the substrate; a base region over the drift layer; multiple source regions over an upper layer portion of the base region; a contact region over the upper layer portion of the base region between opposing source regions; multiple trenches from a surface of each source region to a depth deeper than the base region; a gate electrode on a gate insulating film in each trench; a source electrode electrically connected to the source regions and the contact region; a drain electrode over a rear surface of the substrate; and multiple electric field relaxation layers in the drift layer between adjacent trenches. Each electric field relaxation layer includes: a first region at a position deeper than the trenches; and a second region from a surface of the drift layer to the first region.

公开(公告)号：US20160133741A1

公开(公告)日：2016-05-12

申请号：US14929742

申请日：2015-11-02

申请人： TOYOTA JIDOSHA KABUSHIKI KAISHA

发明人： Hideo MATSUKI ,  Jun SAKAKIBARA ,  Sachiko AOI ,  Yukihiko WATANABE ,  Atsushi ONOGI

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L29/06 ,  H01L29/16 ,  H01L29/10

CPC分类号： H01L29/7813 ,  H01L29/0619 ,  H01L29/063 ,  H01L29/0661 ,  H01L29/0869 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/66734 ,  H01L29/7811

摘要： A silicon carbide semiconductor device includes a MOSFET and a peripheral high-breakdown-voltage structure. A source region has a first recess. Trenches extend from the bottom of the first recess. A gate insulating film has an extension the shape of which follows the shape of the first recess. The surface of a gate electrode is positioned to be flush with or below the upper surface of the extension.

摘要翻译： 碳化硅半导体器件包括MOSFET和外围高击穿电压结构。 源极区域具有第一凹部。 沟槽从第一凹槽的底部延伸。 栅极绝缘膜具有其形状跟第一凹部的形状的延伸。 栅电极的表面定位成与延伸部的上表面齐平或下方。

公开(公告)号：US20150041850A1

公开(公告)日：2015-02-12

申请号：US14513685

申请日：2014-10-14

申请人： DENSO CORPORATION

发明人： Hirotaka SAIKAKU ,  Tsuyoshi YAMAMOTO ,  Shoji MIZUNO ,  Masakiyo SUMITOMO ,  Tetsuo FUJII ,  Jun SAKAKIBARA ,  Hitoshi YAMAGUCHI ,  Yoshiyuki HATTORI ,  Rie TAGUCHI ,  Makoto KUWAHARA

IPC分类号： H01L27/06 ,  H01L29/10 ,  H01L29/78 ,  H01L29/423 ,  H01L29/739

CPC分类号： H01L29/7813 ,  H01L27/0629 ,  H01L27/0635 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/4983 ,  H01L29/66734 ,  H01L29/7391 ,  H01L29/7393 ,  H01L29/7397 ,  H01L29/7398 ,  H01L29/7805 ,  H01L29/7819 ,  H01L29/7825 ,  H01L29/7831 ,  H01L29/861 ,  H01L2924/0002 ,  H02M7/003 ,  H01L2924/00

摘要： A semiconductor device includes a switching element having: a drift layer; a base region; an element-side first impurity region in the base region; an element-side gate electrode sandwiched between the first impurity region and the drift layer; a second impurity region contacting the drift layer; an element-side first electrode coupled with the element-side first impurity region and the base region; and an element-side second electrode coupled with the second impurity region, and a FWD having: a first conductive layer; a second conductive layer; a diode-side first electrode coupled to the second conductive layer; a diode-side second electrode coupled to the first conductive layer; a diode-side first impurity region in the second conductive layer; and a diode-side gate electrode in the second conductive layer sandwiched between first impurity region and the first conductive layer and having a first gate electrode as an excess carrier injection suppression gate.

摘要翻译： 一种半导体器件包括：具有漂移层的开关元件; 基地区 在基极区域中的元件侧第一杂质区域; 夹在所述第一杂质区域和所述漂移层之间的元件侧栅电极; 接触漂移层的第二杂质区; 与元件侧第一杂质区域和基极区域耦合的元件侧第一电极; 以及与所述第二杂质区域耦合的元件侧第二电极以及具有：第一导电层的FWD; 第二导电层; 耦合到所述第二导电层的二极管侧第一电极; 耦合到所述第一导电层的二极管侧第二电极; 第二导电层中的二极管侧第一杂质区; 以及夹在第一杂质区域和第一导电层之间的第二导电层中的二极管侧栅电极，并具有作为过剩载流子注入抑制栅极的第一栅极电极。

公开(公告)号：US20170012109A1

公开(公告)日：2017-01-12

申请号：US15113484

申请日：2015-01-14

申请人： DENSO CORPORATION

发明人： Nozomu AKAGI ,  Jun SAKAKIBARA ,  Shoji MIZUNO ,  Yuichi TAKEUCHI

IPC分类号： H01L29/66 ,  H01L21/04 ,  H01L23/544 ,  H01L29/08 ,  H01L29/423 ,  H01L29/417 ,  H01L29/16 ,  H01L29/10

CPC分类号： H01L29/66068 ,  H01L21/0465 ,  H01L21/0475 ,  H01L23/544 ,  H01L29/0865 ,  H01L29/1033 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/36 ,  H01L29/41741 ,  H01L29/4236 ,  H01L29/66734 ,  H01L29/7813 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for manufacturing a SiC semiconductor device includes: forming recesses to be separated from each other on a cross section in parallel to a surface of the substrate by partially removing a top portion of the drift layer with etching using a mask after arranging the mask on a front surface of a drift layer; forming electric field relaxation layers having the second conductivity type to be separated from each other on the cross section by ion-implanting a second conductivity type impurity on a bottom of each recess using the mask; and forming a channel layer by forming a second conductivity type layer on the front surface of the drift layer including a front surface of each electric field relaxation layer in a respective recess.

摘要翻译： 一种制造SiC半导体器件的方法包括：通过在将掩模布置在其上之后通过使用掩模进行蚀刻部分去除漂移层的顶部而在与基板的表面平行的横截面上形成彼此分离的凹槽 漂移层的前表面; 通过使用掩模在每个凹部的底部上离子注入第二导电型杂质，形成具有第二导电类型的电场弛豫层，以在截面上彼此分离; 以及通过在所述漂移层的前表面上形成第二导电类型层，形成沟道层，所述第二导电类型层包括各个凹槽中每个电场弛豫层的前表面。