公开(公告)号：US20160233226A1

公开(公告)日：2016-08-11

申请号：US14799779

申请日：2015-07-15

Applicant: Kabushiki Kaisha Toshiba

Inventor： Takeshi MURATA

IPC: H01L27/115 ,  H01L21/283 ,  H01L21/28

CPC classification number: H01L27/11524 ,  H01L29/40114

Abstract: A method of manufacturing a semiconductor memory device according to an embodiment comprises: stacking a first insulating layer on a semiconductor layer, the first insulating layer being provided with a first region, a second region, and a third region that are adjacent in a first direction; stacking a charge accumulation layer formation layer; stacking a second insulating layer; and stacking a first conductive layer. The method comprises: in the second region on the semiconductor layer, removing the first insulating layer, the charge accumulation layer formation layer, the second insulating layer, and the first conductive layer to expose the semiconductor layer. Moreover, the method comprises: stacking in the second region a third insulating layer; and stacking a second conductive layer. Furthermore, the method comprises: exposing an upper surface of the semiconductor layer in the third region.

Abstract translation: 根据实施例的制造半导体存储器件的方法包括：在半导体层上堆叠第一绝缘层，所述第一绝缘层设置有第一区域，第二区域和第三区域，所述第一区域，第二区域和第三区域在第一方向 ; 层叠电荷累积层形成层; 堆叠第二绝缘层; 并堆叠第一导电层。 该方法包括：在半导体层的第二区域中，去除第一绝缘层，电荷累积层形成层，第二绝缘层和第一导电层，以暴露半导体层。 此外，该方法包括：在第二区域中堆叠第三绝缘层; 并堆叠第二导电层。 此外，该方法包括：在第三区域中暴露半导体层的上表面。

公开(公告)号：US20150041815A1

公开(公告)日：2015-02-12

申请号：US14195022

申请日：2014-03-03

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Takeshi SONEHARA ,  Takeshi MURATA ,  Junya FUJITA ,  Fumiki AISO ,  Saku HASHIURA

IPC: H01L29/788 ,  H01L29/66

CPC classification number: H01L29/66825 ,  H01L21/28273 ,  H01L27/11529 ,  H01L27/11534 ,  H01L29/513 ,  H01L29/518 ,  H01L29/7881

Abstract: According to one embodiment, a plurality of memory cell transistors including a floating gate and a control gate and a plurality of peripheral circuit transistors including a lower electrode portion and an upper electrode portion are included. The floating gate includes a first polysilicon region, and the lower electrode includes a second polysilicon region. The first polysilicon region is a p-type semiconductor in which boron is doped, and the second polysilicon region is an n-type semiconductor in which phosphorus and boron are doped.

Abstract translation: 根据一个实施例，包括包括浮动栅极和控制栅极的多个存储单元晶体管和包括下电极部分和上电极部分的多个外围电路晶体管。 浮置栅极包括第一多晶硅区域，下部电极包括第二多晶硅区域。 第一多晶硅区域是其中掺杂有硼的p型半导体，并且第二多晶硅区域是掺杂有磷和硼的n型半导体。

公开(公告)号：US20140293694A1

公开(公告)日：2014-10-02

申请号：US14301102

申请日：2014-06-10

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Takeshi KAMIGAICHI ,  Takeshi MURATA ,  Itaru KAWABATA

IPC: G11C16/04 ,  G11C5/06

CPC classification number: H01L27/11519 ,  G11C5/06 ,  G11C5/063 ,  G11C16/04 ,  G11C16/0483 ,  H01L27/115 ,  H01L27/11524

Abstract: A nonvolatile semiconductor memory includes a cell unit having a select gate transistor and a memory cell connected in series, a select gate line connected to the select gate transistor, and a word line connected to the memory cell. One end of the word line is bent to the select gate line side, and a fringe is connected between a bent point and a distal end of the word line.

Abstract translation: 非易失性半导体存储器包括具有选择栅极晶体管和串联连接的存储单元的单元单元，连接到选择栅极晶体管的选择栅极线和连接到存储单元的字线。 字线的一端弯曲到选择栅线侧，并且边缘连接在字线的弯曲点和远端之间。

公开(公告)号：US20160071863A1

公开(公告)日：2016-03-10

申请号：US14638615

申请日：2015-03-04

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Akio KANEKO ,  Wataru SAKAMOTO ,  Takeshi MURATA

IPC: H01L27/115 ,  H01L21/265 ,  H01L21/324 ,  H01L21/3115 ,  H01L21/02

CPC classification number: H01L21/26513 ,  H01L21/31155 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11536 ,  H01L27/11539 ,  H01L27/11541 ,  H01L27/11543

Abstract: A method of manufacturing a semiconductor storage apparatus according to an embodiment includes forming an array of a plurality of memory cells. The method includes forming an interlayer insulating film that covers the memory cells. The method includes forming a first nitride film that covers an upper part of the interlayer insulating film. The method includes ion-implanting a first impurity into the first nitride film.

Abstract translation: 根据实施例的制造半导体存储装置的方法包括形成多个存储单元的阵列。 该方法包括形成覆盖存储单元的层间绝缘膜。 该方法包括形成覆盖层间绝缘膜的上部的第一氮化物膜。 该方法包括将第一杂质离子注入到第一氮化物膜中。

公开(公告)号：US20160064393A1

公开(公告)日：2016-03-03

申请号：US14938888

申请日：2015-11-12

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Takeshi KAMIGAICHI ,  Takeshi MURATA ,  ltaru KAWABATA

IPC: H01L27/115

CPC classification number: H01L27/11519 ,  G11C5/06 ,  G11C5/063 ,  G11C16/04 ,  G11C16/0483 ,  H01L27/115 ,  H01L27/11524

Abstract: A nonvolatile semiconductor memory includes a cell unit having a select gate transistor and a memory cell connected in series, a select gate line connected to the select gate transistor, and a word line connected to the memory cell. One end of the word line is bent to the select gate line side, and a fringe is connected between a bent point and a distal end of the word line.

公开(公告)号：US20150162340A1

公开(公告)日：2015-06-11

申请号：US14626566

申请日：2015-02-19

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Takeshi KAMIGAICHI ,  Takeshi MURATA ,  Itaru KAWABATA

IPC: H01L27/115 ,  G11C5/06

CPC classification number: H01L27/11519 ,  G11C5/06 ,  G11C5/063 ,  G11C16/04 ,  G11C16/0483 ,  H01L27/115 ,  H01L27/11524

Abstract: A nonvolatile semiconductor memory includes a cell unit having a select gate transistor and a memory cell connected in series, a select gate line connected to the select gate transistor, and a word line connected to the memory cell. One end of the word line is bent to the select gate line side, and a fringe is connected between a bent point and a distal end of the word line.

Abstract translation: 非易失性半导体存储器包括具有选择栅极晶体管和串联连接的存储单元的单元单元，连接到选择栅极晶体管的选择栅极线和连接到存储单元的字线。 字线的一端弯曲到选择栅线侧，并且边缘连接在字线的弯曲点和远端之间。

公开(公告)号：US20170271527A1

公开(公告)日：2017-09-21

申请号：US15280013

申请日：2016-09-29

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Masaaki HIGUCHI ,  Masao SHINGU ,  Tatsuya KATO ,  Takeshi MURATA ,  Makoto FUJIWARA ,  Masaki KONDO ,  Muneyuki TSUDA ,  Takashi KURUSU

IPC: H01L29/792 ,  H01L23/522 ,  G11C16/08 ,  H01L29/10 ,  G11C16/26 ,  H01L27/115 ,  H01L23/528

CPC classification number: H01L29/7923 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/26 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/1037

Abstract: A semiconductor memory device includes a substrate, a multi-layered structure including a plurality of insulating layers and a plurality of conductive layers that are alternately formed above the substrate, and a pillar extending through the multi-layered structure. The pillar includes a semiconductor body extending along the pillar, and a charge-storing film around the semiconductor body, the charge-storing film having a first thickness at first portions facing the insulating layers and a second thickness greater than the first thickness at second portions facing the conductive layers.

公开(公告)号：US20160043196A1

公开(公告)日：2016-02-11

申请号：US14624541

申请日：2015-02-17

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Takeshi MURATA ,  Nobuhito KUGE

IPC: H01L29/49 ,  H01L27/115 ,  H01L29/66 ,  H01L29/788

CPC classification number: H01L29/4941 ,  H01L21/28518 ,  H01L21/76805 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76855 ,  H01L23/485 ,  H01L23/53266 ,  H01L27/11524 ,  H01L29/42376 ,  H01L29/4925 ,  H01L29/665

Abstract: According to an embodiment, a semiconductor device includes a semiconductor element that is formed on a semiconductor substrate, an interlayer insulating film, including a silicon oxide film, that is formed to cover the semiconductor element, a wiring layer, including a metal, that is formed in the interlayer insulating film, and a first metal silicide film that is formed between the wiring layer and the interlayer insulating film.

Abstract translation: 根据实施例，半导体器件包括形成在半导体衬底上的半导体元件，形成为覆盖半导体元件的包括氧化硅膜的层间绝缘膜，包括金属的布线层，即， 形成在所述层间绝缘膜中，以及形成在所述布线层和所述层间绝缘膜之间的第一金属硅化物膜。