公开(公告)号：US20160268379A1

公开(公告)日：2016-09-15

申请号：US14849748

申请日：2015-09-10

Applicant: Kabushiki Kaisha Toshiba

Inventor： Hiroyuki YAMASAKI ,  Makoto FUJIWARA ,  Shinji MORI

IPC: H01L29/10 ,  H01L21/02 ,  H01L21/324 ,  H01L27/115

CPC classification number: H01L29/1054 ,  H01L21/28282 ,  H01L21/324 ,  H01L27/11582

Abstract: One embodiment includes: forming a laminated body by alternately laminating a conducting layer and an interlayer insulating layer on a substrate; forming a memory hole passing through the laminated body; forming a memory gate insulating layer including a charge storage layer on an inner wall of the memory hole; forming a first semiconductor layer on the memory gate insulating layer; forming a cover film on the first semiconductor layer; removing the memory gate insulating layer, the first semiconductor layer, and the cover film on a bottom surface of the memory hole, to expose the substrate; forming an epitaxial layer on the exposed substrate; removing the cover film; and forming the second semiconductor layer along the first semiconductor layer, to electrically couple: the substrate to the first semiconductor layer; and the substrate to the second semiconductor layer, via the epitaxial layer.

Abstract translation: 一个实施例包括：通过在基板上交替层叠导电层和层间绝缘层来形成层压体; 形成通过层叠体的记忆孔; 在所述存储孔的内壁上形成包含电荷存储层的存储栅极绝缘层; 在所述存储器栅极绝缘层上形成第一半导体层; 在所述第一半导体层上形成覆盖膜; 在存储孔的底面上去除存储栅极绝缘层，第一半导体层和覆盖膜，以露出衬底; 在所述暴露的基板上形成外延层; 去除覆盖膜; 以及沿着所述第一半导体层形成所述第二半导体层，以将所述衬底电耦合到所述第一半导体层; 以及通过外延层到第二半导体层的衬底。

公开(公告)号：US20160197094A1

公开(公告)日：2016-07-07

申请号：US15072895

申请日：2016-03-17

Applicant: Kabushiki Kaisha Toshiba

Inventor： Masaaki HIGUCHI ,  Katsuyuki SEKINE ,  Makoto FUJIWARA

IPC: H01L27/115

CPC classification number: H01L27/11582 ,  H01L27/11556

Abstract: According to one embodiment, a non-volatile memory device includes electrodes, one semiconductor layer, conductive layers, and first and second insulating films. The electrodes are arranged side by side in a first direction. The semiconductor layer extends into the electrodes in the first direction. The conductive layers are provided between each electrode and the semiconductor layer and separated from each other in the first direction. The first insulating film extends between the conductive layers and the semiconductor layer in the first direction. The second insulating film is provided between each electrode and the conductive layers. The conductive layers become smaller in a thickness as the conductive layers are closer to an end in the first direction or a direction opposite to the first direction. The second insulating film includes a first film contacting the conductive layers, and a second film provided between each electrode and the first film.

公开(公告)号：US20170062451A1

公开(公告)日：2017-03-02

申请号：US15046054

申请日：2016-02-17

Applicant: Kabushiki Kaisha Toshiba

Inventor： Masao SHINGU ,  Katsuyuki SEKINE ,  Hirokazu ISHIGAKI ,  Makoto FUJIWARA

IPC: H01L27/115

CPC classification number: H01L27/11563 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/11582 ,  H01L28/00

Abstract: A semiconductor memory device includes first and second electrode films, an interlayer insulating film, a semiconductor pillar, and a first insulating film. The first electrode film extends in a first direction. The second electrode film is provided separately from the first electrode film in a second direction and extends in the first direction. The interlayer insulating film is provided between the first and the second electrode films. The first insulating film includes first and second insulating regions. A concentration of nitrogen in the first position of the second insulating region is higher than a concentration of nitrogen in the second position between the first position and the semiconductor pillar. A concentration of nitrogen in the first insulating region is lower than the concentration of the nitrogen in the first position.

Abstract translation: 半导体存储器件包括第一和第二电极膜，层间绝缘膜，半导体柱和第一绝缘膜。 第一电极膜沿第一方向延伸。 第二电极膜沿第二方向与第一电极膜分开设置并沿第一方向延伸。 层间绝缘膜设置在第一和第二电极膜之间。 第一绝缘膜包括第一和第二绝缘区域。 第二绝缘区域的第一位置的氮浓度高于第一位置和半导体柱之间的第二位置的氮浓度。 第一绝缘区域中的氮浓度低于第一位置的氮浓度。

公开(公告)号：US20150372002A1

公开(公告)日：2015-12-24

申请号：US14483546

申请日：2014-09-11

Applicant: Kabushiki Kaisha Toshiba

Inventor： Masaaki HIGUCHI ,  Katsuyuki SEKINE ,  Makoto FUJIWARA

IPC: H01L27/115

CPC classification number: H01L27/11582 ,  H01L27/11556

Abstract: According to one embodiment, a non-volatile memory device includes electrodes, one semiconductor layer, conductive layers, and first and second insulating films. The electrodes are arranged side by side in a first direction. The semiconductor layer extends into the electrodes in the first direction. The conductive layers are provided between each electrode and the semiconductor layer and separated from each other in the first direction. The first insulating film extends between the conductive layers and the semiconductor layer in the first direction. The second insulating film is provided between each electrode and the conductive layers. The conductive layers become smaller in a thickness as the conductive layers are closer to an end in the first direction or a direction opposite to the first direction. The second insulating film includes a first film contacting the conductive layers, and a second film provided between each electrode and the first film.

Abstract translation: 根据一个实施例，非易失性存储器件包括电极，一个半导体层，导电层以及第一和第二绝缘膜。 电极沿第一方向并排配置。 半导体层沿第一方向延伸到电极中。 导电层设置在每个电极和半导体层之间，并且在第一方向上彼此分离。 第一绝缘膜在第一方向上在导电层和半导体层之间延伸。 第二绝缘膜设置在每个电极和导电层之间。 当导电层靠近第一方向或与第一方向相反的方向的端部时，导电层的厚度变小。 第二绝缘膜包括与导电层接触的第一膜，以及设置在每个电极和第一膜之间的第二膜。

公开(公告)号：US20170077125A1

公开(公告)日：2017-03-16

申请号：US15045526

申请日：2016-02-17

Applicant: Kabushiki Kaisha Toshiba

Inventor： Hiroyuki YAMASAKI ,  Makoto FUJIWARA ,  Daisuke NISHIDA

IPC: H01L27/115 ,  H01L29/04 ,  H01L21/02 ,  H01L29/10

CPC classification number: H01L27/11582 ,  H01L21/02233 ,  H01L27/1157 ,  H01L29/04 ,  H01L29/1037

Abstract: According to one embodiment, a semiconductor memory device includes a substrate; a stacked body including a plurality of insulating layers and including a first insulating layer and a plurality of conductive layers including a first conductive layer; a first semiconductor film extending in a stacking direction of the stacked body; a second semiconductor film, the second semiconductor film having a maximum thickness thicker than a maximum thickness of the first semiconductor film in a first direction crossing the stacking direction; and a first insulating film. The second semiconductor film has an upper face, and a height of the upper face is lower than a height of the first conductive layer. The first insulating film has a lower end portion, and a height of the lower end portion of the first insulating film is lower than the height of the upper face of the second semiconductor film.

Abstract translation: 根据一个实施例，半导体存储器件包括衬底; 包括多个绝缘层并且包括第一绝缘层和包括第一导电层的多个导电层的堆叠体; 沿层叠体的堆叠方向延伸的第一半导体膜; 第二半导体膜，所述第二半导体膜在与所述堆叠方向交叉的第一方向上具有比所述第一半导体膜的最大厚度厚的最大厚度; 和第一绝缘膜。 第二半导体膜具有上表面，上表面的高度低于第一导电层的高度。 第一绝缘膜具有下端部，第一绝缘膜的下端部的高度比第二半导体膜的上表面的高度低。

公开(公告)号：US20170271527A1

公开(公告)日：2017-09-21

申请号：US15280013

申请日：2016-09-29

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Masaaki HIGUCHI ,  Masao SHINGU ,  Tatsuya KATO ,  Takeshi MURATA ,  Makoto FUJIWARA ,  Masaki KONDO ,  Muneyuki TSUDA ,  Takashi KURUSU

IPC: H01L29/792 ,  H01L23/522 ,  G11C16/08 ,  H01L29/10 ,  G11C16/26 ,  H01L27/115 ,  H01L23/528

CPC classification number: H01L29/7923 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/26 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/1037

Abstract: A semiconductor memory device includes a substrate, a multi-layered structure including a plurality of insulating layers and a plurality of conductive layers that are alternately formed above the substrate, and a pillar extending through the multi-layered structure. The pillar includes a semiconductor body extending along the pillar, and a charge-storing film around the semiconductor body, the charge-storing film having a first thickness at first portions facing the insulating layers and a second thickness greater than the first thickness at second portions facing the conductive layers.