公开(公告)号：US20170243873A1

公开(公告)日：2017-08-24

申请号：US15269082

申请日：2016-09-19

Applicant: Kabushiki Kaisha Toshiba

Inventor： Shigeki KOBAYASHI ,  Satoshi KONAGAI ,  Atsushi KONNO ,  Kenta YAMADA ,  Masaaki HIGUCHI ,  Masao SHINGU ,  Soichiro KITAZAKI ,  Yoshimasa MIKAJIRI

IPC: H01L27/115 ,  H01L29/51 ,  H01L21/768 ,  H01L21/285 ,  H01L21/28 ,  H01L29/423 ,  H01L29/49

CPC classification number: H01L27/11582 ,  H01L21/28088 ,  H01L21/28114 ,  H01L21/28158 ,  H01L21/28556 ,  H01L21/76831 ,  H01L28/00 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/518

Abstract: According to an embodiment, a semiconductor memory device comprises: a stacked body including control gate electrodes stacked upwardly of a substrate; a semiconductor layer facing the control gate electrodes; and a gate insulating layer provided between the control gate electrode and the semiconductor layer. The stacked body comprises: a first metal layer configuring the control gate electrode; a first barrier metal layer contacting an upper surface of this first metal layer; a first silicon nitride layer contacting an upper surface of this first barrier metal layer; a first inter-layer insulating layer contacting an upper surface of this first silicon nitride layer; a second barrier metal layer contacting a lower surface of the first metal layer; a second silicon nitride layer contacting a lower surface of this second barrier metal layer; and a second inter-layer insulating layer contacting a lower surface of this second silicon nitride layer.

公开(公告)号：US20160315092A1

公开(公告)日：2016-10-27

申请号：US15201708

申请日：2016-07-05

Applicant: Kabushiki Kaisha Toshiba

Inventor： Masaaki HIGUCHI ,  Katsuyuki SEKINE ,  Fumiki AISO ,  Takuo OHASHI ,  Tatsuya OKAMOTO

IPC: H01L27/115 ,  H01L21/02

CPC classification number: H01L27/11556 ,  H01L21/0262 ,  H01L21/02636 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/7785

Abstract: According to one embodiment, a non-volatile memory device includes a plurality of electrodes, at least one semiconductor layer, conductive layers, and first and second insulating films. The electrodes are arranged side by side in a first direction. The semiconductor layer extends into the electrodes in the first direction. The conductive layers are provided between each electrode and the semiconductor layer and separated from each other in the first direction. The first insulating film contacts the conductive layers, and extends in the first direction along the semiconductor layer between the conductive layers and the semiconductor layer. The second insulating film is provided between the first insulating film and the semiconductor layer. The first insulating film includes a first portion located between the conductive layers and the second insulating film, and a second portion located between the interlayer insulating film and the second insulating film.

公开(公告)号：US20150371997A1

公开(公告)日：2015-12-24

申请号：US14483697

申请日：2014-09-11

Applicant: Kabushiki Kaisha Toshiba

Inventor： Masaaki HIGUCHI ,  Katsuyuki SEKINE ,  Fumiki AlSO ,  Tatsuya OKAMOTO ,  Masaru KITO

IPC: H01L27/115 ,  H01L29/66 ,  H01L29/423 ,  H01L21/02 ,  H01L29/51 ,  H01L21/28 ,  H01L21/311 ,  H01L29/788 ,  H01L29/49

CPC classification number: H01L27/11556 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11582

Abstract: According to one embodiment, a non-volatile memory device includes electrodes, one semiconductor layer, conductive layers, and first and second insulating films. The electrodes are arranged side by side in a first direction. The semiconductor layer extends into the electrodes in the first direction. The conductive layers are provided between each electrode and the semiconductor layer and separated from each other in the first direction. The first insulating film extends between the conductive layers and the semiconductor layer in the first direction. The second insulating film is provided between each electrode and the conductive layers. The conductive layers become smaller in a thickness as the conductive layers are closer to an end in the first direction or a direction opposite to the first direction.

Abstract translation: 根据一个实施例，非易失性存储器件包括电极，一个半导体层，导电层以及第一和第二绝缘膜。 电极沿第一方向并排配置。 半导体层沿第一方向延伸到电极中。 导电层设置在每个电极和半导体层之间，并且在第一方向上彼此分离。 第一绝缘膜在第一方向上在导电层和半导体层之间延伸。 第二绝缘膜设置在每个电极和导电层之间。 当导电层靠近第一方向或与第一方向相反的方向的端部时，导电层的厚度变小。

公开(公告)号：US20140252453A1

公开(公告)日：2014-09-11

申请号：US14284638

申请日：2014-05-22

Applicant: Kabushiki Kaisha Toshiba

Inventor： Masaaki HIGUCHI ,  Yoshio Ozawa ,  Katsuyuki Sekine ,  Ryota Fujitsuka

IPC: H01L29/792

CPC classification number: H01L29/792 ,  H01L21/28282 ,  H01L29/4234 ,  H01L29/513 ,  H01L29/66833

Abstract: According to one embodiment, a nonvolatile semiconductor memory device including a semiconductor layer with a main surface, a first insulating layer formed on the main surface of the semiconductor layer, a charge storage layer formed on the first insulating layer, a second insulating layer formed on the charge storage layer, and a control gate electrode formed on the second insulating layer. At least one inelastic scattering film that reduces energy of electrons by scattering is contained in at least one of the charge storage layer and second insulating layer.

Abstract translation: 根据一个实施例，一种非易失性半导体存储器件，包括具有主表面的半导体层，形成在半导体层的主表面上的第一绝缘层，形成在第一绝缘层上的电荷存储层，形成在第一绝缘层上的第二绝缘层 电荷存储层和形成在第二绝缘层上的控制栅电极。 至少一个通过散射减少电子能量的非弹性散射膜被包含在电荷存储层和第二绝缘层中的至少一个中。

公开(公告)号：US20170271527A1

公开(公告)日：2017-09-21

申请号：US15280013

申请日：2016-09-29

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Masaaki HIGUCHI ,  Masao SHINGU ,  Tatsuya KATO ,  Takeshi MURATA ,  Makoto FUJIWARA ,  Masaki KONDO ,  Muneyuki TSUDA ,  Takashi KURUSU

IPC: H01L29/792 ,  H01L23/522 ,  G11C16/08 ,  H01L29/10 ,  G11C16/26 ,  H01L27/115 ,  H01L23/528

CPC classification number: H01L29/7923 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/26 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/1037

Abstract: A semiconductor memory device includes a substrate, a multi-layered structure including a plurality of insulating layers and a plurality of conductive layers that are alternately formed above the substrate, and a pillar extending through the multi-layered structure. The pillar includes a semiconductor body extending along the pillar, and a charge-storing film around the semiconductor body, the charge-storing film having a first thickness at first portions facing the insulating layers and a second thickness greater than the first thickness at second portions facing the conductive layers.

公开(公告)号：US20170117293A1

公开(公告)日：2017-04-27

申请号：US15398230

申请日：2017-01-04

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Masaaki HIGUCHI ,  Masaru KITO ,  Masao SHINGU

IPC: H01L27/11582 ,  H01L27/1157

CPC classification number: H01L27/11582 ,  H01L27/1157 ,  H01L29/66833 ,  H01L29/7926

Abstract: According to an embodiment, a non-volatile storage device includes a first layer, a second layer formed on the first layer, a stacked body including a plurality of conductive films stacked on the second layer, and a semiconductor pillar which penetrates the stacked body and the second layer and reaches the first layer. The semiconductor pillar includes a semiconductor film formed along an extending direction of the semiconductor pillar, and a memory film which covers a periphery of the semiconductor film. The memory film includes a first portion formed between the stacked body and the semiconductor film and a second portion formed between the second layer and the semiconductor film. An outer periphery of the second portion in a plane perpendicular to the extending direction is wider than an outer periphery of the first portion on a second layer side of the stacked body.

公开(公告)号：US20160079257A1

公开(公告)日：2016-03-17

申请号：US14844382

申请日：2015-09-03

Applicant: Kabushiki Kaisha Toshiba

Inventor： Takeshi SONEHARA ,  Takahiro HIRAI ,  Masaaki HIGUCHI ,  Takashi SHIMIZU

IPC: H01L27/115 ,  H01L21/321 ,  H01L21/3213

CPC classification number: H01L21/32105 ,  H01L27/11582

Abstract: According to an embodiment, a nonvolatile semiconductor memory device comprises a plurality of conductive layers that are stacked in plurality in a first direction via an inter-layer insulating layer, that extend in a second direction which intersects the first direction, and that are disposed in plurality in a third direction which intersects the first direction and the second direction. In addition, the same nonvolatile semiconductor memory device comprises: a semiconductor layer that has the first direction as a longitudinal direction; a tunnel insulating layer that contacts a side surface of the semiconductor layer; a charge accumulation layer that contacts a side surface of the tunnel insulating layer; and a block insulating layer that contacts a side surface of the charge accumulation layer. Furthermore, in the same nonvolatile semiconductor memory device, an end in the third direction of the plurality of conductive layers is rounded.

Abstract translation: 根据一个实施例，非易失性半导体存储器件包括多个导电层，它们经由层间绝缘层沿第一方向多个堆叠，其沿与第一方向相交的第二方向延伸，并且被布置在 在与第一方向和第二方向相交的第三方向上多个。 另外，相同的非易失性半导体存储器件包括：具有第一方向作为纵向方向的半导体层; 与所述半导体层的侧面接触的隧道绝缘层; 与隧道绝缘层的侧表面接触的电荷累积层; 以及与电荷蓄积层的侧面接触的块绝缘层。 此外，在相同的非易失性半导体存储器件中，多个导电层的第三方向上的端部是圆形的。

公开(公告)号：US20160064408A1

公开(公告)日：2016-03-03

申请号：US14805954

申请日：2015-07-22

Applicant: Kabushiki Kaisha Toshiba

Inventor： Masao SHINGU ,  Masaaki HIGUCHI ,  Katsuyuki SEKINE ,  Kazuhiro MATSUO

IPC: H01L27/115 ,  H01L29/51 ,  H01L29/423

CPC classification number: H01L27/11582 ,  H01L27/1157

Abstract: According to an embodiment, a nonvolatile semiconductor memory device comprises: a plurality of conductive layers stacked in a first direction via an inter-layer insulating layer; a semiconductor layer having the first direction as a longer direction; a tunnel insulating layer contacting a side surface of the semiconductor layer; a charge accumulation layer contacting a side surface of the tunnel insulating layer; and a block insulating layer contacting a side surface of the charge accumulation layer. The inter-layer insulating layer comprises: a first silicon oxide layer; a first metal oxide layer; and a first silicon nitride layer. The first metal oxide layer is formed on a first surface facing the conductive layer, of the first silicon oxide layer. The first silicon nitride layer is formed on the first surface via the first metal oxide layer.

Abstract translation: 根据一个实施例，非易失性半导体存储器件包括：经由层间绝缘层沿第一方向堆叠的多个导电层; 具有作为长方向的第一方向的半导体层; 与半导体层的侧面接触的隧道绝缘层; 与隧道绝缘层的侧表面接触的电荷累积层; 以及与电荷累积层的侧表面接触的块绝缘层。 层间绝缘层包括：第一氧化硅层; 第一金属氧化物层; 和第一氮化硅层。 第一金属氧化物层形成在第一氧化硅层的面向导电层的第一表面上。 第一氮化硅层经由第一金属氧化物层形成在第一表面上。

公开(公告)号：US20160197094A1

公开(公告)日：2016-07-07

申请号：US15072895

申请日：2016-03-17

Applicant: Kabushiki Kaisha Toshiba

Inventor： Masaaki HIGUCHI ,  Katsuyuki SEKINE ,  Makoto FUJIWARA

IPC: H01L27/115

CPC classification number: H01L27/11582 ,  H01L27/11556

Abstract: According to one embodiment, a non-volatile memory device includes electrodes, one semiconductor layer, conductive layers, and first and second insulating films. The electrodes are arranged side by side in a first direction. The semiconductor layer extends into the electrodes in the first direction. The conductive layers are provided between each electrode and the semiconductor layer and separated from each other in the first direction. The first insulating film extends between the conductive layers and the semiconductor layer in the first direction. The second insulating film is provided between each electrode and the conductive layers. The conductive layers become smaller in a thickness as the conductive layers are closer to an end in the first direction or a direction opposite to the first direction. The second insulating film includes a first film contacting the conductive layers, and a second film provided between each electrode and the first film.

公开(公告)号：US20160013201A1

公开(公告)日：2016-01-14

申请号：US14863749

申请日：2015-09-24

Applicant: Kabushiki Kaisha Toshiba

Inventor： Masaaki HIGUCHI ,  Katsuyuki SEKINE ,  Fumiki AISO ,  Takuo OHASHI ,  Tatsuya OKAMOTO

IPC: H01L27/115

CPC classification number: H01L27/11556 ,  H01L21/0262 ,  H01L21/02636 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/7785

Abstract: According to one embodiment, a non-volatile memory device includes a plurality of electrodes, at least one semiconductor layer, conductive layers, and first and second insulating films. The electrodes are arranged side by side in a first direction. The semiconductor layer extends into the electrodes in the first direction. The conductive layers are provided between each electrode and the semiconductor layer and separated from each other in the first direction. The first insulating film contacts the conductive layers, and extends in the first direction along the semiconductor layer between the conductive layers and the semiconductor layer. The second insulating film is provided between the first insulating film and the semiconductor layer. The first insulating film includes a first portion located between the conductive layers and the second insulating film, and a second portion located between the interlayer insulating film and the second insulating film.

Abstract translation: 根据一个实施例，非易失性存储器件包括多个电极，至少一个半导体层，导电层以及第一和第二绝缘膜。 电极沿第一方向并排配置。 半导体层沿第一方向延伸到电极中。 导电层设置在每个电极和半导体层之间，并且在第一方向上彼此分离。 第一绝缘膜与导电层接触，沿导电层和半导体层之间的半导体层在第一方向上延伸。 第二绝缘膜设置在第一绝缘膜和半导体层之间。 第一绝缘膜包括位于导电层和第二绝缘膜之间的第一部分和位于层间绝缘膜和第二绝缘膜之间的第二部分。