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    METHOD OF MANUFACTURING A LAMINATE CIRCUIT BOARD
    3.
    发明申请
    METHOD OF MANUFACTURING A LAMINATE CIRCUIT BOARD 审中-公开
    制造层压板电路板的方法

    公开(公告)号：US20130255858A1

    公开(公告)日：2013-10-03

    申请号：US13437933

    申请日：2012-04-03

    Applicant: Jun-Chung Hsu ,  Chi-Ming Lin ,  Tso-Hung Yeh ,  Ya-Hsiang Chen

    Inventor： Jun-Chung Hsu ,  Chi-Ming Lin ,  Tso-Hung Yeh ,  Ya-Hsiang Chen

    IPC: B32B38/10 ,  B32B38/08

    CPC classification number: H05K3/282 ,  H05K1/0366 ,  H05K3/103 ,  H05K3/146 ,  H05K3/16 ,  H05K3/202 ,  H05K3/244 ,  H05K3/381 ,  H05K3/384 ,  H05K2201/0376 ,  H05K2201/09227 ,  H05K2203/0152 ,  H05K2203/0278 ,  H05K2203/072 ,  Y10T156/10

    Abstract: A method of manufacturing a laminate circuit board is disclosed. The method includes forming a metal layer on a substrate, patterning the metal layer to form a circuit metal layer, forming a nanometer plating layer with a thickness of 5 to 40 nm over the circuit metal layer, and forming a cover layer covering the substrate and the nanometer plating layer with improved adhesion by chemical bonding to form the laminate circuit board. Another method includes forming the circuit metal layer and the nanometer plating layer on a preforming substrate, pressing the preforming substrate against a substrate to push the circuit metal layer and the nanometer plating layer into the substrate, and removing the preforming substrate. By the present invention, the density of circuit is increased and much denser circuit can be implemented on the substrate with the same area.

    Abstract translation: 公开了一种制造叠层电路板的方法。 该方法包括在基板上形成金属层，图案化金属层以形成电路金属层，在电路金属层上形成厚度为5至40nm的纳米电镀层，并形成覆盖基板的覆盖层和 纳米电镀层通过化学键合具有改善的粘附性以形成层压电路板。 另一种方法包括在预成型基板上形成电路金属层和纳米电镀层，将预成型基板压靠在基板上，将电路金属层和纳米电镀层推入基板，以及去除预成形基板。 通过本发明，电路的密度增加，并且可以在具有相同面积的基板上实现更加密集的电路。

    Method For Fabricating Carrier Board Having No Conduction Line
    4.
    发明申请
    Method For Fabricating Carrier Board Having No Conduction Line 审中-公开
    制造无导通线的载板的方法

    公开(公告)号：US20110061234A1

    公开(公告)日：2011-03-17

    申请号：US12548418

    申请日：2009-09-15

    Applicant: Jun-Chung Hsu ,  Yi-Fan Kao

    Inventor： Jun-Chung Hsu ,  Yi-Fan Kao

    IPC: H05K3/10

    CPC classification number: H05K3/242 ,  H05K3/205 ,  H05K3/244 ,  H05K3/423 ,  H05K2203/0726 ,  H05K2203/0733 ,  H05K2203/1581 ,  Y10T29/49155

    Abstract: A method for fabricating a carrier board having no conduction line is provided. The fabricating method includes: providing a support plate having a detachable metal layer; providing a plating current via the support plate and the detachable metal layer to plate on the detachable metal layer to in sequence configure an etching resist layer and a plating metal layer; and then gradually completing other circuit layers by a compression laminating process with the support plate providing the plating current. After the entire plating process has been completed, the support plate and the detachable metal layer are removed.

    Abstract translation: 提供了一种制造不具有导线的载板的方法。 制造方法包括：提供具有可拆卸金属层的支撑板; 通过所述支撑板和所述可拆卸金属层在可拆卸金属层上提供电镀电流，以依次配置抗蚀剂层和电镀金属层; 然后通过压缩层压工艺逐渐完成其它电路层，其中支撑板提供电镀电流。 在整个电镀工艺完成之后，移除支撑板和可拆卸的金属层。

    Solder Pad Structure With High Bondability To Solder Ball
    5.
    发明申请
    Solder Pad Structure With High Bondability To Solder Ball 有权
    焊接接头结构与焊球接合性高

    公开(公告)号：US20110048782A1

    公开(公告)日：2011-03-03

    申请号：US12547495

    申请日：2009-08-26

    Applicant: Jun-Chung Hsu

    Inventor： Jun-Chung Hsu

    IPC: H05K1/11 ,  B44C1/22

    CPC classification number: H05K1/111 ,  H01L2224/05557 ,  H05K3/062 ,  H05K3/3452 ,  H05K3/4007 ,  H05K2201/0338 ,  H05K2201/0367 ,  H05K2201/0373 ,  H05K2201/09745 ,  H05K2201/099 ,  H05K2203/1184 ,  Y02P70/611 ,  Y10T29/4913 ,  Y10T29/49156

    Abstract: A solder pad structure with a high bondability to a solder ball is provided. The present invention provides a larger contact area with the solder ball so as to increase the bondability according to the principle that the bondability is positive proportional with the contact area therebetween. The solder pad structure includes a circuit board having a solder pad opening defined by a solder resist layer surrounding a circuit layer. The circuit layer within the solder pad opening is defined as a solder pad. In such a way, after filling the solder ball into the solder pad opening, besides walls of the solder pad opening, there are an extra contact area provided by a geometric shape of the solder pad for further improving the bondability of the solder pad and the solder ball.

    Abstract translation: 提供了与焊球具有高粘合性的焊盘结构。 本发明提供了一种与焊球相比较大的接触面积，以便根据粘合性与它们之间的接触面积成正比的原理提高粘接性。 焊盘结构包括具有由围绕电路层的阻焊层限定的焊盘开口的电路板。 焊盘开口内的电路层被定义为焊盘。 以这种方式，在将焊球填充到焊盘开口中之后，除了焊盘开口的壁之外，还存在由焊料焊盘的几何形状提供的额外的接触面积，用于进一步提高焊盘和焊盘的焊接性 焊球

    LAMINATE CIRCUIT BOARD STRUCTURE
    6.
    发明申请
    LAMINATE CIRCUIT BOARD STRUCTURE 审中-公开
    层压电路板结构

    公开(公告)号：US20130284500A1

    公开(公告)日：2013-10-31

    申请号：US13455364

    申请日：2012-04-25

    Applicant: Jun-Chung Hsu ,  Chi-Ming Lin ,  Tso-Hung Yeh ,  Ya-Hsiang Chen

    Inventor： Jun-Chung Hsu ,  Chi-Ming Lin ,  Tso-Hung Yeh ,  Ya-Hsiang Chen

    IPC: H05K1/03 ,  H05K1/02

    CPC classification number: H05K3/388 ,  H05K3/381 ,  H05K2203/0307

    Abstract: A laminate circuit board structure from button up including a substrate, a circuit metal layer, a nanometer plating layer and a cover layer is disclosed. The nanometer plating layer is smooth a thickness of 5-40 nm, and can be directly forming on the outer surface of the circuit metal layer or manufactured by firstly forming the nanometer plating layer on a preforming substrate, then pressing the substrate against the nanometer plating layer, and finally removing the preforming substrate. The junction adhesion between the nanometer plating layer and the cover layer or the substrate is improved by chemical bonding. Therefore it does not need to roughen the circuit metal layer or reserve circuit width for compensation such that the density of the circuit increases and much more dense circuit can be implemented in the substrate with the same area.

    Abstract translation: 公开了一种按钮的层叠电路板结构，包括基板，电路金属层，纳米电镀层和覆盖层。 纳米电镀层的光滑厚度为5-40nm，可以直接形成在电路金属层的外表面上，或者通过首先在预成型基板上形成纳米镀层，然后将衬底压在纳米电镀上 层，最后除去预成型基板。 通过化学键合可以改善纳米镀层与覆盖层或衬底之间的结合性。 因此，不需要粗糙化电路金属层或补偿电路宽度，使得电路的密度增加，并且可以在具有相同面积的基板中实现更加密集的电路。

    Flip-Chip Package Structure
    7.
    发明申请
    Flip-Chip Package Structure 审中-公开
    倒装芯片封装结构

    公开(公告)号：US20110049703A1

    公开(公告)日：2011-03-03

    申请号：US12547475

    申请日：2009-08-25

    Applicant: Jun-Chung Hsu ,  Shuo-Hsun Chang

    Inventor： Jun-Chung Hsu ,  Shuo-Hsun Chang

    IPC: H01L23/498

    CPC classification number: H01L23/49811 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00

    Abstract: A flip-chip (FC) package structure is provided. The FC package structure includes a substrate, a chip, a plurality of copper platforms, a plurality of copper bumps, a plating layer, a circuit layer and a solder mask layer. The copper bumps are disposed on the substrate. The copper platforms are stacked on the copper bumps. The plating layer covers the copper bumps and the copper platforms, for contacting with chip foot pads configured at a bottom of the chip. The FC package structure does not need to reserve a space for wire bonding, thus saving the area of the substrate. The copper platforms are stacked on the copper bumps, and are higher than the circuit pattern layer. Therefore, the chip is blocked up, and the gap between the chip and the substrate is enlarged, thus preventing the risk of configuring voids when filling the cladding material and improving the packaging yield.

    Abstract translation: 提供了倒装芯片（FC）封装结构。 FC封装结构包括基板，芯片，多个铜平台，多个铜凸块，镀层，电路层和焊料掩模层。 铜凸块设置在基板上。 铜平台堆叠在铜凸块上。 电镀层覆盖铜凸块和铜平台，用于与配置在芯片底部的芯片脚垫接触。 FC封装结构不需要预留用于引线接合的空间，从而节省了基板的面积。 铜平台堆叠在铜凸块上，并且高于电路图案层。 因此，芯片被堵塞，并且芯片和基板之间的间隙扩大，从而防止在填充包层材料时配置空隙的风险并提高包装产量。

    Solder pad structure with high bondability to solder ball
    8.
    发明授权
    Solder pad structure with high bondability to solder ball 有权
    焊锡焊接结构，焊接性好

    公开(公告)号：US08315063B2

    公开(公告)日：2012-11-20

    申请号：US12547495

    申请日：2009-08-26

    Applicant: Jun-Chung Hsu

    Inventor： Jun-Chung Hsu

    IPC: H05K7/00

    CPC classification number: H05K1/111 ,  H01L2224/05557 ,  H05K3/062 ,  H05K3/3452 ,  H05K3/4007 ,  H05K2201/0338 ,  H05K2201/0367 ,  H05K2201/0373 ,  H05K2201/09745 ,  H05K2201/099 ,  H05K2203/1184 ,  Y02P70/611 ,  Y10T29/4913 ,  Y10T29/49156

    Abstract: A solder pad structure with a high bondability to a solder ball is provided. The present invention provides a larger contact area with the solder ball so as to increase the bondability according to the principle that the bondability is positive proportional with the contact area therebetween. The solder pad structure includes a circuit board having a solder pad opening defined by a solder resist layer surrounding a circuit layer. The circuit layer within the solder pad opening is defined as a solder pad. In such a way, after filling the solder ball into the solder pad opening, besides walls of the solder pad opening, there is an extra contact area provided by a geometric shape of the solder pad for further improving the bondability of the solder pad and the solder ball.

    Abstract translation: 提供了与焊球具有高粘合性的焊盘结构。 本发明提供了一种与焊球相比较大的接触面积，以便根据粘合性与它们之间的接触面积成正比的原理提高粘接性。 焊盘结构包括具有由围绕电路层的阻焊层限定的焊盘开口的电路板。 焊盘开口内的电路层被定义为焊盘。 以这种方式，在将焊球填充到焊盘开口中之后，除了焊盘开口的壁之外，还存在由焊料焊盘的几何形状提供的额外的接触面积，用于进一步提高焊盘的焊接性和 焊球

    Method for manufacturing carrier substrate
    9.
    发明授权
    Method for manufacturing carrier substrate 有权
    制造载体基板的方法

    公开(公告)号：US07662662B2

    公开(公告)日：2010-02-16

    申请号：US11685751

    申请日：2007-03-13

    Applicant: Jun-Chung Hsu ,  Bing-Kuen Lin ,  Chao-Lung Wang

    Inventor： Jun-Chung Hsu ,  Bing-Kuen Lin ,  Chao-Lung Wang

    IPC: H01L21/00 ,  H01L21/44

    CPC classification number: H05K3/421 ,  H05K1/116 ,  H05K3/108 ,  H05K3/426 ,  H05K2201/09545 ,  H05K2201/09563 ,  Y10T29/49162

    Abstract: A carrier substrate and a method for manufacturing the carrier substrate are disclosed herein. The method includes the steps of: providing a core substrate; forming a build-up material layer on the core substrate; forming a via in the build-up material layer; forming a patterned photoresist layer on the build-up material layer covering a portion of the via and exposing an opening from uncovered portion of the via, and a wiring slot connected to the opening; and forming a metal-electroplated layer on the via and the wiring slot. In forming a trace according to the present invention, the metal-electroplated layer is formed as the trace and directly connected to the via, striding or not striding over the via. Additionally, in the carrier substrate structure, there is no need an annular ring to connect the trace to the via, and thus the wiring space is increased.

    Abstract translation: 本文公开了载体基板和用于制造载体基板的方法。 该方法包括以下步骤：提供芯基板; 在所述芯基板上形成积层材料层; 在积层材料层中形成通孔; 在所述积层材料层上形成图案化的光致抗蚀剂层，所述图案化的光致抗蚀剂层覆盖所述通孔的一部分，并且从所述通孔的未覆盖部分露出开口，以及连接到所述开口的布线槽; 以及在通孔和布线槽上形成金属电镀层。 在形成根据本发明的迹线的情况下，金属电镀层形成为迹线，并且直接连接到通孔，跨越通道或跨过通孔。 此外，在载体基板结构中，不需要环形环来将迹线连接到通孔，因此布线空间增加。

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