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    Tunable high impedance surface device
    1.
    发明授权
    Tunable high impedance surface device 失效
    可调高阻抗表面装置

    公开(公告)号：US07518465B2

    公开(公告)日：2009-04-14

    申请号：US11616061

    申请日：2006-12-26

    申请人： Jovica Savic ,  Gregory J. Dunn ,  John A. Svigelj

    发明人： Jovica Savic ,  Gregory J. Dunn ,  John A. Svigelj

    IPC分类号： H01P1/06 ,  H01P5/04 ,  H01Q1/38

    CPC分类号： H05K1/162 ,  H01G5/18 ,  H01Q15/0066 ,  H01Q15/147 ,  H05K1/116 ,  H05K3/0023 ,  H05K3/4652 ,  H05K2201/0195 ,  H05K2201/09109 ,  H05K2201/09436 ,  H05K2201/096 ,  Y10T29/49117

    摘要： A tunable high impedance surface device (100) includes a conductive ground plane (105) and a plurality of conductive elements (110-114) electrically connected to the conductive ground plane (105). The device (100) also includes a plurality of capacitive elements (120-124) operable to vary a predetermined electromagnetic characteristic of the apparatus and standoffs (130, 132) between the plurality of capacitive elements (120-124) and the plurality of conductive elements (110-114). In one form, laser-drilled and electrically conductive micro-vias (136, 138) extend through the standoffs (130, 132) thereby electrically connecting the plurality of capacitive elements (120-124) to a data bus (140). The capacitive elements (120-124) may be integral with a circuit board (144) that supports the plurality conductive elements (110-114). Either the capacitive elements (120-124) or the conductive elements (110-114) are mechanically flexible and selectively movable to controllably adjust the distance (142) between the capacitive and conductive elements.

    摘要翻译： 可调谐高阻抗表面器件（100）包括导电接地平面（105）和电连接到导电接地平面（105）的多个导电元件（110-114）。 设备（100）还包括多个电容元件（120-124），可操作以改变设备的预定电磁特性和多个电容元件（120-124）与多个导电（120-124）之间的支座（130,132） 元素（110-114）。 在一种形式中，激光钻孔和导电微通孔（136,138）延伸穿过支座（130,132），从而将多个电容元件（120-124）电连接到数据总线（140）。 电容元件（120-124）可以与支撑多个导电元件（110-114）的电路板（144）成一体。 电容元件（120-124）或导电元件（110-114）中的任何一个都是机械地柔性的并且选择性地可移动以可控地调节电容元件和导电元件之间的距离（142）。

    TUNABLE HIGH IMPEDANCE SURFACE DEVICE
    2.
    发明申请
    TUNABLE HIGH IMPEDANCE SURFACE DEVICE 失效
    高阻抗表面装置

    公开(公告)号：US20080150657A1

    公开(公告)日：2008-06-26

    申请号：US11616061

    申请日：2006-12-26

    申请人： Jovica Savic ,  Gregory J. Dunn ,  John A. Svigelj

    发明人： Jovica Savic ,  Gregory J. Dunn ,  John A. Svigelj

    IPC分类号： H01P1/10 ,  H01P7/00 ,  H01R43/00

    CPC分类号： H05K1/162 ,  H01G5/18 ,  H01Q15/0066 ,  H01Q15/147 ,  H05K1/116 ,  H05K3/0023 ,  H05K3/4652 ,  H05K2201/0195 ,  H05K2201/09109 ,  H05K2201/09436 ,  H05K2201/096 ,  Y10T29/49117

    摘要： A tunable high impedance surface device (100) includes a conductive ground plane (105) and a plurality of conductive elements (110-114) electrically connected to the conductive ground plane (105). The device (100) also includes a plurality of capacitive elements (120-124) operable to vary a predetermined electromagnetic characteristic of the apparatus and standoffs (130, 132) between the plurality of capacitive elements (120-124) and the plurality of conductive elements (110-114). In one form, laser-drilled and electrically conductive micro-vias (136, 138) extend through the standoffs (130, 132) thereby electrically connecting the plurality of capacitive elements (120-124) to a data bus (140). The capacitive elements (120-124) may be integral with a circuit board (144) that supports the plurality conductive elements (110-114). Either the capacitive elements (120-124) or the conductive elements (110-114) are mechanically flexible and selectively movable to controllably adjust the distance (142) between the capacitive and conductive elements.

    摘要翻译： 可调谐高阻抗表面器件（100）包括导电接地平面（105）和电连接到导电接地平面（105）的多个导电元件（110-114）。 装置（100）还包括多个电容元件（120-124），可操作以改变装置的预定电磁特性和多个电容元件（120-124）之间的间隔（130,132）和多个导电 元素（110 - 114）。 在一种形式中，激光钻孔和导电微通孔（136,138）延伸穿过支座（130,132），从而将多个电容元件（120-124）电连接到数据总线（140）。 电容元件（120-124）可以与支撑多个导电元件（110-114）的电路板（144）成一体。 电容元件（120-124）或导电元件（110-114）中的任何一个都是机械地柔性的并且选择性地可移动以可控地调节电容元件和导电元件之间的距离（142）。

    Textured dielectric patch antenna fabrication method
    3.
    发明授权
    Textured dielectric patch antenna fabrication method 失效
    纹理电介质贴片天线制造方法

    公开(公告)号：US07337528B2

    公开(公告)日：2008-03-04

    申请号：US11021444

    申请日：2004-12-23

    申请人： Gregory J. Dunn ,  Jovica Savic ,  John A. Svigelj ,  Nadia Yala

    发明人： Gregory J. Dunn ,  Jovica Savic ,  John A. Svigelj ,  Nadia Yala

    IPC分类号： H01P11/00

    CPC分类号： H01Q9/0407 ,  Y10T29/49016 ,  Y10T29/49117 ,  Y10T29/49165

    摘要： A textured dielectric patch antenna is fabricated by applying a first mask pattern (310, 510, 610, 710, 915, 1015, 1210) to a first side of a solid panel made of a first material that is a ceramic dielectric and then sandblasting the solid panel through the first mask pattern from the first side to at least partially generate a shaped cavity (315, 920, 1040). The shaped cavity of the solid panel may be filled with a second material (330, 740). The first and second materials have substantially differing dielectric constants. The first side and second side of the solid panel are metallized (325), forming a patch antenna. The shaped cavities can be made more complex by using additional masking and/or sandblasting steps.

    摘要翻译： 通过将第一掩模图案（310,510,610,710,915,1015,1210）施加到由作为陶瓷电介质的第一材料制成的实心面板的第一侧上，然后对其进行喷砂来制造纹理化介质贴片天线 通过第一掩模图案从第一侧至少部分地产生成形腔（315,920,1040）。 固体面板的成形腔可以填充有第二材料（330,740）。 第一和第二材料具有基本上不同的介电常数。 固体面板的第一侧面和第二侧被金属化（325），形成贴片天线。 通过使用额外的掩模和/或喷砂步骤，可使成形的空腔变得更加复杂。

    Method for manufacturing an integral thin-film metal resistor
    6.
    发明授权
    Method for manufacturing an integral thin-film metal resistor 失效
    制造整体薄膜金属电阻的方法

    公开(公告)号：US06232042B1

    公开(公告)日：2001-05-15

    申请号：US09111189

    申请日：1998-07-07

    申请人： Gregory J. Dunn ,  Jovica Savic ,  Allyson Beuhler

    发明人： Gregory J. Dunn ,  Jovica Savic ,  Allyson Beuhler

    IPC分类号： G03F700

    CPC分类号： H05K1/167 ,  G03F7/00 ,  H01C17/07 ,  H05K3/0023 ,  H05K3/025 ,  H05K3/048 ,  H05K3/386 ,  H05K2201/0317 ,  H05K2201/09881 ,  H05K2203/0152 ,  H05K2203/1461

    摘要： A method for manufacturing a microelectronic assembly to have a resistor, and particularly a metal resistive film, with desirable processing and dimensional characteristics. The method generally entails applying a photosensitive dielectric to a substrate to form a dielectric layer. The dielectric layer is photoimaged to polymerize a first portion of the dielectric layer on a first region of the substrate, leaving the remainder of the dielectric layer unpolymerized. An electrically resistive film is then applied to the dielectric layer, and the dielectric layer is developed to remove concurrently the unpolymerized portion thereof and the portion of the resistive film overlying the unpolymerized portion, so that a portion of the resistive film remains over the second portion to form the resistor. An alternative process order is to apply the resistive film prior to exposing the dielectric layer to radiation, and then exposing the dielectric layer through the resistive film. The resistive film is preferably a multilayer film that includes an electrically resistive layer, such as NiP, NiCr or another nickel-containing alloy, and a sacrificial backing such as a layer of copper.

    摘要翻译： 一种用于制造具有所需加工和尺寸特性的电阻器，特别是金属电阻膜的微电子组件的方法。 该方法通常需要将光敏电介质施加到衬底以形成电介质层。 介电层被光刻以在基板的第一区域上聚合电介质层的第一部分，留下介电层的其余部分未聚合。 然后将电阻膜施加到电介质层，并且电介质层被显影以同时除去其未聚合部分和覆盖未聚合部分的电阻膜的部分，使得电阻膜的一部分保留在第二部分上 以形成电阻器。 替代的处理顺序是在将电介质层暴露于辐射之前施加电阻膜，然后将电介质层暴露于电阻膜。 电阻膜优选为包含电阻层的多层膜，例如NiP，NiCr或其它含镍合金，以及牺牲衬底，例如铜层。

    Circuit board features with reduced parasitic capacitance and method therefor
    10.
    发明授权
    Circuit board features with reduced parasitic capacitance and method therefor 失效
    电路板具有降低的寄生电容及其方法

    公开(公告)号：US6103134A

    公开(公告)日：2000-08-15

    申请号：US224011

    申请日：1998-12-31

    申请人： Gregory J. Dunn ,  Larry Lach ,  Jovica Savic ,  Allyson Beuhler ,  Everett Simons

    发明人： Gregory J. Dunn ,  Larry Lach ,  Jovica Savic ,  Allyson Beuhler ,  Everett Simons

    IPC分类号： H01F17/00 ,  H01F41/04 ,  H01L21/768 ,  H01L23/522 ,  H05K1/16 ,  H05K3/00 ,  H05K3/06 ,  H05K3/46

    CPC分类号： H05K3/0082 ,  H01F41/041 ,  H01F41/046 ,  H05K1/165 ,  H05K3/0023 ,  H01F17/0013 ,  H05K2201/0187 ,  H05K2201/0355 ,  H05K2201/086 ,  H05K2201/09236 ,  H05K2203/0551 ,  H05K3/4652

    摘要： A method for fabricating circuit board conductors with desirable processing and reduced self and mutual capacitance. The method generally entails forming a metal layer on a positive-acting photodielectric layer formed on a substrate, and then etching the metal layer to form at least two conductor traces that cover two separate regions of the photodielectric layer while exposing a third region of the photodielectric layer between the two regions. The third region of the photodielectric layer is then irradiated and developed using the two traces as a photomask, so that the third region of the photodielectric layer is removed. The two remaining regions of the photodielectric layer masked by the traces remain on the substrate and are separated by an opening formed by the removal of the third dielectric region. As a result, the traces are not only separated by a void immediately therebetween formed when the metal layer was etched, but are also separated by the opening formed in the photodielectric layer by the removal of the third region of the photodielectric layer. Traces formed in accordance with the above may be formed as adjacent and parallel conductors or adjacent inductor windings of an integral inductor.

    摘要翻译： 一种用于制造具有所需加工和减小的自相互电容的电路板导体的方法。 该方法通常需要在形成在衬底上的正性作用的光致电介质层上形成金属层，然后蚀刻金属层以形成覆盖光致介电层的两个分离区域的至少两个导体迹线，同时暴露光致介电层的第三区域 两个地区之间。 然后使用两条迹线作为光掩模来照射和显影光致电介质层的第三区域，从而去除光致电介质层的第三区域。 由迹线掩蔽的光电介质层的两个剩余区域保留在基板上，并由通过去除第三介电区域形成的开口分开。 结果，痕迹不仅仅在金属层被蚀刻时形成的空隙之间分开，而且还通过去除光致电介质层的第三区域而被形成在光致电介质层中的开口分开。 根据上述形成的迹线可以形成为整体电感器的相邻和平行的导体或相邻的电感器绕组。