公开(公告)号：US20090124075A1

公开(公告)日：2009-05-14

申请号：US12149014

申请日：2008-04-24

申请人： Joon-Seok Kang ,  Sung Yi ,  Jong-Hwan Baek ,  Young-Do Kweon

发明人： Joon-Seok Kang ,  Sung Yi ,  Jong-Hwan Baek ,  Young-Do Kweon

IPC分类号： H01L21/768

CPC分类号： H01L24/13 ,  H01L24/11 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05147 ,  H01L2224/05611 ,  H01L2224/11334 ,  H01L2224/1147 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/16 ,  H01L2924/00013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00

摘要： A method of manufacturing a wafer level package is disclosed, which may include: coating an insulation layer over one side of a semiconductor chip, on one side of which an electrode pad is formed, such that the electrode pad is open; forming a seed layer by depositing a conductive metal onto one side of the semiconductor chip; forming a rewiring pattern that is electrically connected with the electrode pad, by selective electroplating with the seed layer as an electrode; forming a conductive pillar that is electrically connected with the rewiring pattern, by selective electroplating with the seed layer as an electrode; and removing portions of the seed layer open to the exterior. By forming the rewiring pattern and the metal pillar using one seed layer, the manufacturing process can be simplified, whereby defects during the manufacturing process can be reduced and the reliability of the products can be improved.

摘要翻译： 公开了一种制造晶片级封装的方法，其可以包括：在半导体芯片的一侧上涂覆绝缘层，其一面形成电极焊盘，使得电极焊盘打开; 通过在所述半导体芯片的一侧上沉积导电金属形成晶种层; 形成与电极焊盘电连接的重新布线图案，通过选择性地电镀种子层作为电极; 形成与所述重新布线图案电连接的导电柱，通过所述种子层作为电极的选择性电镀; 并将种子层的部分去除到外部。 通过使用一个种子层形成再布线图案和金属柱，可以简化制造工艺，从而可以减少制造过程中的缺陷，并且可以提高产品的可靠性。

公开(公告)号：US07727877B2

公开(公告)日：2010-06-01

申请号：US12149014

申请日：2008-04-24

申请人： Joon-Seok Kang ,  Sung Yi ,  Jong-Hwan Baek ,  Young-Do Kweon

发明人： Joon-Seok Kang ,  Sung Yi ,  Jong-Hwan Baek ,  Young-Do Kweon

IPC分类号： H01L21/445

CPC分类号： H01L24/13 ,  H01L24/11 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05147 ,  H01L2224/05611 ,  H01L2224/11334 ,  H01L2224/1147 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/16 ,  H01L2924/00013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00

摘要： A method of manufacturing a wafer level package is disclosed, which may include: coating an insulation layer over one side of a semiconductor chip, on one side of which an electrode pad is formed, such that the electrode pad is open; forming a seed layer by depositing a conductive metal onto one side of the semiconductor chip; forming a rewiring pattern that is electrically connected with the electrode pad, by selective electroplating with the seed layer as an electrode; forming a conductive pillar that is electrically connected with the rewiring pattern, by selective electroplating with the seed layer as an electrode; and removing portions of the seed layer open to the exterior. By forming the rewiring pattern and the metal pillar using one seed layer, the manufacturing process can be simplified, whereby defects during the manufacturing process can be reduced and the reliability of the products can be improved.

摘要翻译： 公开了一种制造晶片级封装的方法，其可以包括：在半导体芯片的一侧上涂覆绝缘层，其一面形成电极焊盘，使得电极焊盘打开; 通过在所述半导体芯片的一侧上沉积导电金属形成晶种层; 形成与电极焊盘电连接的重新布线图案，通过选择性地电镀种子层作为电极; 形成与所述重新布线图案电连接的导电柱，通过所述种子层作为电极的选择性电镀; 并将种子层的部分去除到外部。 通过使用一个种子层形成再布线图案和金属柱，可以简化制造工艺，从而可以减少制造过程中的缺陷，并且可以提高产品的可靠性。

公开(公告)号：US20090302468A1

公开(公告)日：2009-12-10

申请号：US12232252

申请日：2008-09-12

申请人： Jong Hwan Baek ,  Sung Yi ,  Young Do Kweon ,  Jong Yun Lee ,  Hyung Jin Jeon ,  Joon Seok Kang

发明人： Jong Hwan Baek ,  Sung Yi ,  Young Do Kweon ,  Jong Yun Lee ,  Hyung Jin Jeon ,  Joon Seok Kang

IPC分类号： H01L23/488 ,  H01L21/56

CPC分类号： H05K3/3436 ,  H01L23/3114 ,  H01L24/11 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05647 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/16 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/181 ,  H05K3/3463 ,  H05K2201/10992 ,  Y02P70/613 ,  H01L2224/13099 ,  H01L2224/29099 ,  H01L2924/00 ,  H01L2924/00014

摘要： Disclosed is a printed circuit board including a semiconductor chip, which includes a semiconductor chip having a connection pad, which is exposed, on the upper surface thereof, a first solder ball formed on the connection pad and having a first melting point, a printed circuit board having an external connection terminal formed at the outermost circuit layer thereof, and a second solder ball formed on the external connection terminal, connected to the first solder ball, and having a second melting point higher than the first melting point. In the printed circuit board including a semiconductor chip, the distance between the printed circuit board and the semiconductor chip is increased, thus realizing high resistance to flexure due to the difference in thermal expansion coefficient between the printed circuit board and the semiconductor chip.

摘要翻译： 公开了一种印刷电路板，其包括半导体芯片，该半导体芯片包括具有连接焊盘的半导体芯片，该连接焊盘在其上表面上露出形成在连接焊盘上并具有第一熔点的第一焊球，印刷电路 板上具有形成在其最外侧电路层的外部连接端子，和形成在外部连接端子上的第二焊球，与第一焊球相连，并具有高于第一熔点的第二熔点。 在包括半导体芯片的印刷电路板中，印刷电路板和半导体芯片之间的距离增加，由于印刷电路板和半导体芯片之间的热膨胀系数的差异，实现了高抗弯曲性。

公开(公告)号：US07663250B2

公开(公告)日：2010-02-16

申请号：US12230793

申请日：2008-09-04

申请人： Hyung Jin Jeon ,  Sung Yi ,  Jong Yun Lee ,  Young Do Kweon ,  Jong Hwan Baek

发明人： Hyung Jin Jeon ,  Sung Yi ,  Jong Yun Lee ,  Young Do Kweon ,  Jong Hwan Baek

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L24/12 ,  H01L24/11 ,  H01L2224/0231 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/13099 ,  H01L2224/13139 ,  H01L2224/16 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/014 ,  H01L2924/30105 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00014

摘要： A wafer level package and a manufacturing method thereof capable of reducing stress between an under bump metal and a bump. The wafer level package includes a substrate provided with a plurality of chip pads on a top surface; a first passivation layer to expose the chip pads; vias connected to the chip pads by passing through the first passivation layer; a metal wiring layer formed on the first passivation layer and connected to the vias; an under bump metal formed on the first passivation layer to be connected to the metal wiring layer and having a buffer pattern separated through a trench on a center; a second passivation layer formed on the first passivation layer to expose the under bump metal; a first bump formed on the buffer pattern; and a second bump filling the trench and formed on the first bump and the under bump metal.

摘要翻译： 一种晶片级封装及其制造方法，能够减少凸块之间的应力。 晶片级封装包括在顶表面上设置有多个芯片焊盘的衬底; 第一钝化层以暴露所述芯片焊盘; 通过穿过第一钝化层连接到芯片焊盘的通孔; 形成在所述第一钝化层上并连接到所述通孔的金属布线层; 形成在所述第一钝化层上以连接到所述金属布线层并且具有通过中心的沟槽分离的缓冲图案的下凸块金属; 形成在所述第一钝化层上以暴露所述下凸块金属的第二钝化层; 形成在缓冲图案上的第一凸起; 以及填充所述沟槽并形成在所述第一凸块和所述下凸块金属上的第二凸块。

公开(公告)号：US20090309216A1

公开(公告)日：2009-12-17

申请号：US12230793

申请日：2008-09-04

申请人： Hyung Jin Jeon ,  Sung Yi ,  Jong Yun Lee ,  Young Do Kweon ,  Jong Hwan Baek

发明人： Hyung Jin Jeon ,  Sung Yi ,  Jong Yun Lee ,  Young Do Kweon ,  Jong Hwan Baek

IPC分类号： H01L23/52 ,  H01L21/00

CPC分类号： H01L24/12 ,  H01L24/11 ,  H01L2224/0231 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/13099 ,  H01L2224/13139 ,  H01L2224/16 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/014 ,  H01L2924/30105 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00014

摘要： A wafer level package and a manufacturing method thereof capable of reducing stress between an under bump metal and a bump. The wafer level package includes a substrate provided with a plurality of chip pads on a top surface; a first passivation layer to expose the chip pads; vias connected to the chip pads by passing through the first passivation layer; a metal wiring layer formed on the first passivation layer and connected to the vias; an under bump metal formed on the first passivation layer to be connected to the metal wiring layer and having a buffer pattern separated through a trench on a center; a second passivation layer formed on the first passivation layer to expose the under bump metal; a first bump formed on the buffer pattern; and a second bump filling the trench and formed on the first bump and the under bump metal.

摘要翻译： 一种晶片级封装及其制造方法，能够减少凸块之间的应力。 晶片级封装包括在顶表面上设置有多个芯片焊盘的衬底; 第一钝化层以暴露所述芯片焊盘; 通过穿过第一钝化层连接到芯片焊盘的通孔; 形成在所述第一钝化层上并连接到所述通孔的金属布线层; 形成在所述第一钝化层上以连接到所述金属布线层并且具有通过中心的沟槽分离的缓冲图案的下凸块金属; 形成在所述第一钝化层上以暴露所述下凸块金属的第二钝化层; 形成在缓冲图案上的第一凸起; 以及填充所述沟槽并形成在所述第一凸块和所述下凸块金属上的第二凸块。

公开(公告)号：US07632709B2

公开(公告)日：2009-12-15

申请号：US12149106

申请日：2008-04-25

申请人： Hyung-Jin Jeon ,  Sung Yi ,  Young-Do Kweon ,  Jong-Yun Lee ,  Joon-Seok Kang ,  Seung-Wook Park

发明人： Hyung-Jin Jeon ,  Sung Yi ,  Young-Do Kweon ,  Jong-Yun Lee ,  Joon-Seok Kang ,  Seung-Wook Park

IPC分类号： H01L21/00

CPC分类号： H01L23/3114 ,  H01L21/6835 ,  H01L24/11 ,  H01L24/12 ,  H01L24/24 ,  H01L24/27 ,  H01L24/82 ,  H01L2221/68372 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/16 ,  H01L2224/24227 ,  H01L2224/274 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01059 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/15153 ,  H01L2924/1517

摘要： A method of manufacturing a wafer level package is disclosed. The method may include stacking an insulation layer over a wafer substrate; processing a via hole in the insulation layer; forming a seed layer over the insulation layer; forming a plating resist, which is in a corresponding relationship with a redistribution pattern, over the seed layer; forming the redistribution pattern, which includes a terminal for external contact, by electroplating; and coupling a conductive ball to the terminal. As multiple redistribution layers can be formed using inexpensive PCB processes, the manufacturing costs can be reduced, and the stability and efficiency of the process can be increased.

公开(公告)号：US20120129297A1

公开(公告)日：2012-05-24

申请号：US13363513

申请日：2012-02-01

申请人： Joon Seok KANG ,  Sung Yi ,  Young Do Kweon

发明人： Joon Seok KANG ,  Sung Yi ,  Young Do Kweon

IPC分类号： H01L21/78

CPC分类号： H01L23/3114 ,  H01L21/56 ,  H01L21/568 ,  H01L24/19 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2224/82 ,  H01L2924/00

摘要： A method of manufacturing a wafer level package including: separating chips by dicing a wafer; forming a removable resin layer in a space between the separated chips and at upper parts thereof; separating the chips by dicing the removable resin layer; mounting the chips separated in a state of being surrounded by the removable resin layer, on a carrier plate; forming a molding material on the carrier plate to cover the removable resin layer; separating the carrier plate from the chips; forming a dielectric layer having redistribution lines connected to the chips, on the chips exposed by separating the carrier plate; and forming a solder resist layer on the dielectric layer to expose portions of the redistribution lines.

摘要翻译： 一种制造晶片级封装的方法，包括：通过切割晶片来分离芯片; 在分离的碎片之间的空间中和在其上部形成可移除的树脂层; 通过切割可去除的树脂层来分离芯片; 将被分离的芯片安装在可移除树脂层周围的状态下; 在载体板上形成模塑材料以覆盖可除去的树脂层; 将载板与芯片分离; 在通过分离载体板而暴露的芯片上形成具有连接到芯片的再分配线的电介质层; 以及在所述电介质层上形成阻焊层以暴露所述再分配线的部分。

公开(公告)号：US08110914B2

公开(公告)日：2012-02-07

申请号：US12318752

申请日：2009-01-07

申请人： Joon Seok Kang ,  Sung Yi ,  Young Do Kweon

发明人： Joon Seok Kang ,  Sung Yi ,  Young Do Kweon

IPC分类号： H01L23/498 ,  H01L21/78

CPC分类号： H01L23/3114 ,  H01L21/56 ,  H01L21/568 ,  H01L24/19 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2224/82 ,  H01L2924/00

摘要： A wafer level package includes a chip, a removable resin layer, a molding material, a dielectric layer, redistribution lines and a solder resist. The removable resin layer is formed to surround side surfaces and a lower surface of the chip. The molding material is formed on the lower surface of the removable resin layer. The dielectric layer is formed over the removable resin layer including the chip and having via holes to expose portions of the chip. The redistribution lines are formed on the dielectric layer including insides of the via holes to be connected to the chip. The solder resist layer is formed on the dielectric layer to expose portions of the redistribution lines.

摘要翻译： 晶片级封装包括芯片，可移除树脂层，成型材料，电介质层，再分布线和阻焊剂。 可移除树脂层形成为围绕芯片的侧表面和下表面。 成型材料形成在可移除树脂层的下表面上。 电介质层形成在包括芯片的可移除树脂层上，并且具有通孔以暴露芯片的部分。 再分配线形成在包括要连接到芯片的通孔的内部的电介质层上。 在电介质层上形成阻焊层以暴露再分布线的部分。

公开(公告)号：US20100193932A1

公开(公告)日：2010-08-05

申请号：US12424514

申请日：2009-04-15

申请人： Joon Seok KANG ,  Sung Yi ,  Young Do Kweon

发明人： Joon Seok KANG ,  Sung Yi ,  Young Do Kweon

IPC分类号： H01L23/48 ,  H01L21/78

CPC分类号： H01L23/5389 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/4334 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05548 ,  H01L2224/12105 ,  H01L2924/00014 ,  H01L2924/01012 ,  H01L2924/01073 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/05599

摘要： Disclosed herein are a wafer level package for heat dissipation and a method of manufacturing the same. The wafer level package includes a heat dissipation plate including a cavity and a hole, a die including a pad disposed in the cavity of the heat dissipation plate in a face-up manner, a thermal conductive adhesive disposed between the die and an inner wall of the cavity and disposed in the hole, and a redistribution layer connected at one end to the pad and at the other end extended. The wafer level package protects the die from external environments and enables the die to be easily flush with the heat dissipation plate.

摘要翻译： 这里公开了用于散热的晶片级封装及其制造方法。 晶片级封装包括包括空腔和孔的散热板，包括以面朝上的方式设置在散热板的空腔中的焊盘的模具，设置在模具和内壁之间的导热粘合剂 空腔并设置在孔中，并且再分配层在一端连接到垫并且在另一端延伸。 晶圆级封装保护模具免受外部环境的影响，使模具能够轻松地与散热板齐平。

公开(公告)号：US20090087951A1

公开(公告)日：2009-04-02

申请号：US12149106

申请日：2008-04-25

申请人： Hyung-Jin Jeon ,  Sung Yi ,  Young-Do Kweon ,  Jong-Yun Lee ,  Joon-Seok Kang ,  Seung-Wook Park

发明人： Hyung-Jin Jeon ,  Sung Yi ,  Young-Do Kweon ,  Jong-Yun Lee ,  Joon-Seok Kang ,  Seung-Wook Park

IPC分类号： H01L21/02

CPC分类号： H01L23/3114 ,  H01L21/6835 ,  H01L24/11 ,  H01L24/12 ,  H01L24/24 ,  H01L24/27 ,  H01L24/82 ,  H01L2221/68372 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/16 ,  H01L2224/24227 ,  H01L2224/274 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01059 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/15153 ,  H01L2924/1517

摘要： A method of manufacturing a wafer level package is disclosed. The method may include stacking an insulation layer over a wafer substrate; processing a via hole in the insulation layer; forming a seed layer over the insulation layer; forming a plating resist, which is in a corresponding relationship with a redistribution pattern, over the seed layer; forming the redistribution pattern, which includes a terminal for external contact, by electroplating; and coupling a conductive ball to the terminal. As multiple redistribution layers can be formed using inexpensive PCB processes, the manufacturing costs can be reduced, and the stability and efficiency of the process can be increased.

摘要翻译： 公开了一种制造晶片级封装的方法。 该方法可以包括在晶片衬底上堆叠绝缘层; 处理绝缘层中的通孔; 在所述绝缘层上形成种子层; 在种子层上形成与再分布图案对应关系的电镀抗蚀剂; 通过电镀形成包括用于外部接触的端子的再分布图案; 并将导电球耦合到端子。 由于可以使用廉价的PCB工艺形成多个再分布层，所以可以降低制造成本，并且可以提高工艺的稳定性和效率。