公开(公告)号：US20090124075A1

公开(公告)日：2009-05-14

申请号：US12149014

申请日：2008-04-24

申请人： Joon-Seok Kang ,  Sung Yi ,  Jong-Hwan Baek ,  Young-Do Kweon

发明人： Joon-Seok Kang ,  Sung Yi ,  Jong-Hwan Baek ,  Young-Do Kweon

IPC分类号： H01L21/768

CPC分类号： H01L24/13 ,  H01L24/11 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05147 ,  H01L2224/05611 ,  H01L2224/11334 ,  H01L2224/1147 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/16 ,  H01L2924/00013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00

摘要： A method of manufacturing a wafer level package is disclosed, which may include: coating an insulation layer over one side of a semiconductor chip, on one side of which an electrode pad is formed, such that the electrode pad is open; forming a seed layer by depositing a conductive metal onto one side of the semiconductor chip; forming a rewiring pattern that is electrically connected with the electrode pad, by selective electroplating with the seed layer as an electrode; forming a conductive pillar that is electrically connected with the rewiring pattern, by selective electroplating with the seed layer as an electrode; and removing portions of the seed layer open to the exterior. By forming the rewiring pattern and the metal pillar using one seed layer, the manufacturing process can be simplified, whereby defects during the manufacturing process can be reduced and the reliability of the products can be improved.

摘要翻译： 公开了一种制造晶片级封装的方法，其可以包括：在半导体芯片的一侧上涂覆绝缘层，其一面形成电极焊盘，使得电极焊盘打开; 通过在所述半导体芯片的一侧上沉积导电金属形成晶种层; 形成与电极焊盘电连接的重新布线图案，通过选择性地电镀种子层作为电极; 形成与所述重新布线图案电连接的导电柱，通过所述种子层作为电极的选择性电镀; 并将种子层的部分去除到外部。 通过使用一个种子层形成再布线图案和金属柱，可以简化制造工艺，从而可以减少制造过程中的缺陷，并且可以提高产品的可靠性。

公开(公告)号：US07727877B2

公开(公告)日：2010-06-01

申请号：US12149014

申请日：2008-04-24

申请人： Joon-Seok Kang ,  Sung Yi ,  Jong-Hwan Baek ,  Young-Do Kweon

发明人： Joon-Seok Kang ,  Sung Yi ,  Jong-Hwan Baek ,  Young-Do Kweon

IPC分类号： H01L21/445

CPC分类号： H01L24/13 ,  H01L24/11 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05147 ,  H01L2224/05611 ,  H01L2224/11334 ,  H01L2224/1147 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/16 ,  H01L2924/00013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00

摘要： A method of manufacturing a wafer level package is disclosed, which may include: coating an insulation layer over one side of a semiconductor chip, on one side of which an electrode pad is formed, such that the electrode pad is open; forming a seed layer by depositing a conductive metal onto one side of the semiconductor chip; forming a rewiring pattern that is electrically connected with the electrode pad, by selective electroplating with the seed layer as an electrode; forming a conductive pillar that is electrically connected with the rewiring pattern, by selective electroplating with the seed layer as an electrode; and removing portions of the seed layer open to the exterior. By forming the rewiring pattern and the metal pillar using one seed layer, the manufacturing process can be simplified, whereby defects during the manufacturing process can be reduced and the reliability of the products can be improved.

摘要翻译： 公开了一种制造晶片级封装的方法，其可以包括：在半导体芯片的一侧上涂覆绝缘层，其一面形成电极焊盘，使得电极焊盘打开; 通过在所述半导体芯片的一侧上沉积导电金属形成晶种层; 形成与电极焊盘电连接的重新布线图案，通过选择性地电镀种子层作为电极; 形成与所述重新布线图案电连接的导电柱，通过所述种子层作为电极的选择性电镀; 并将种子层的部分去除到外部。 通过使用一个种子层形成再布线图案和金属柱，可以简化制造工艺，从而可以减少制造过程中的缺陷，并且可以提高产品的可靠性。

公开(公告)号：US07632709B2

公开(公告)日：2009-12-15

申请号：US12149106

申请日：2008-04-25

申请人： Hyung-Jin Jeon ,  Sung Yi ,  Young-Do Kweon ,  Jong-Yun Lee ,  Joon-Seok Kang ,  Seung-Wook Park

发明人： Hyung-Jin Jeon ,  Sung Yi ,  Young-Do Kweon ,  Jong-Yun Lee ,  Joon-Seok Kang ,  Seung-Wook Park

IPC分类号： H01L21/00

CPC分类号： H01L23/3114 ,  H01L21/6835 ,  H01L24/11 ,  H01L24/12 ,  H01L24/24 ,  H01L24/27 ,  H01L24/82 ,  H01L2221/68372 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/16 ,  H01L2224/24227 ,  H01L2224/274 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01059 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/15153 ,  H01L2924/1517

摘要： A method of manufacturing a wafer level package is disclosed. The method may include stacking an insulation layer over a wafer substrate; processing a via hole in the insulation layer; forming a seed layer over the insulation layer; forming a plating resist, which is in a corresponding relationship with a redistribution pattern, over the seed layer; forming the redistribution pattern, which includes a terminal for external contact, by electroplating; and coupling a conductive ball to the terminal. As multiple redistribution layers can be formed using inexpensive PCB processes, the manufacturing costs can be reduced, and the stability and efficiency of the process can be increased.

公开(公告)号：US20090087951A1

公开(公告)日：2009-04-02

申请号：US12149106

申请日：2008-04-25

申请人： Hyung-Jin Jeon ,  Sung Yi ,  Young-Do Kweon ,  Jong-Yun Lee ,  Joon-Seok Kang ,  Seung-Wook Park

发明人： Hyung-Jin Jeon ,  Sung Yi ,  Young-Do Kweon ,  Jong-Yun Lee ,  Joon-Seok Kang ,  Seung-Wook Park

IPC分类号： H01L21/02

CPC分类号： H01L23/3114 ,  H01L21/6835 ,  H01L24/11 ,  H01L24/12 ,  H01L24/24 ,  H01L24/27 ,  H01L24/82 ,  H01L2221/68372 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/16 ,  H01L2224/24227 ,  H01L2224/274 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01059 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/15153 ,  H01L2924/1517

摘要： A method of manufacturing a wafer level package is disclosed. The method may include stacking an insulation layer over a wafer substrate; processing a via hole in the insulation layer; forming a seed layer over the insulation layer; forming a plating resist, which is in a corresponding relationship with a redistribution pattern, over the seed layer; forming the redistribution pattern, which includes a terminal for external contact, by electroplating; and coupling a conductive ball to the terminal. As multiple redistribution layers can be formed using inexpensive PCB processes, the manufacturing costs can be reduced, and the stability and efficiency of the process can be increased.

摘要翻译： 公开了一种制造晶片级封装的方法。 该方法可以包括在晶片衬底上堆叠绝缘层; 处理绝缘层中的通孔; 在所述绝缘层上形成种子层; 在种子层上形成与再分布图案对应关系的电镀抗蚀剂; 通过电镀形成包括用于外部接触的端子的再分布图案; 并将导电球耦合到端子。 由于可以使用廉价的PCB工艺形成多个再分布层，所以可以降低制造成本，并且可以提高工艺的稳定性和效率。

公开(公告)号：US20090253259A1

公开(公告)日：2009-10-08

申请号：US12222967

申请日：2008-08-20

申请人： Jingli Yuan ,  Young-Do Kweon ,  Jae-Kwang Lee ,  Jong-Hwan Baek ,  Hyung-Jin Jeon ,  Seung-Wook Park

发明人： Jingli Yuan ,  Young-Do Kweon ,  Jae-Kwang Lee ,  Jong-Hwan Baek ,  Hyung-Jin Jeon ,  Seung-Wook Park

IPC分类号： H01L21/60 ,  B23K37/04

CPC分类号： B23K1/0016 ,  H01L21/6835 ,  H01L24/11 ,  H01L2224/0231 ,  H01L2224/02333 ,  H01L2224/0401 ,  H01L2224/11003 ,  H01L2224/11334 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/014

摘要： Disclosed are a solder attachment jig and a method of manufacturing a semiconductor device using the same. The solder ball attachment jig, which arranges a solder ball to be aligned with a conductive post of a semiconductor wafer, can include a body and a receiving hole, which is formed on the body to hold the solder ball. Internal walls of the receiving hole that face each other are symmetrically inclined. Using the solder ball attachment jig in accordance with an embodiment of the present invention, the alignment of the solder ball can be improved while reducing the cost and simplifying the processes.

摘要翻译： 公开了焊接附着夹具和使用其的半导体器件的制造方法。 布置焊球与半导体晶片的导电柱对准的焊球附着夹具可以包括主体和容纳孔，其形成在主体上以保持焊球。 相互面对的接收孔的内壁对称地倾斜。 使用根据本发明的实施例的焊球附着夹具，可以提高焊球的对准，同时降低成本并简化工艺。

公开(公告)号：US09209101B2

公开(公告)日：2015-12-08

申请号：US12892032

申请日：2010-09-28

申请人： Do-Jae Yoo ,  Young-Do Kweon ,  Joon-Seok Kang ,  Chang-Bae Lee

发明人： Do-Jae Yoo ,  Young-Do Kweon ,  Joon-Seok Kang ,  Chang-Bae Lee

IPC分类号： H01L23/552 ,  H01L23/31 ,  H01L23/498 ,  H01L23/50 ,  H01L23/00

CPC分类号： H01L23/3121 ,  H01L23/49811 ,  H01L23/50 ,  H01L23/552 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73257 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package and a method of manufacturing the semiconductor package are disclosed. A semiconductor package in accordance with an embodiment of the present invention includes a substrate, which is formed with a ground circuit and mounted with a semiconductor chip on one surface, a conductive ground layer, which is formed on the other surface of the substrate and connected with the ground circuit, a molding, which seals up the ground layer and the substrate having the semiconductor chip mounted thereon, and a conductive shield, which covers the molding and is connected with the ground layer. With a semiconductor package in accordance with an embodiment of the present invention, grounding for shielding is possible even in an entirely molded structure, and a double shielding structure to improve the shielding property.

摘要翻译： 公开了一种半导体封装和半导体封装的制造方法。 根据本发明的实施例的半导体封装包括形成有接地电路并且在一个表面上安装有半导体芯片的基板，形成在基板的另一表面上并连接的导电接地层 接地电路，密封接地层和其上安装有半导体芯片的基板的模制件和覆盖模制件并与接地层连接的导电屏蔽件。 利用根据本发明的实施例的半导体封装，即使在完全模制的结构中也可以进行屏蔽的接地，以及用于提高屏蔽性的双重屏蔽结构。

公开(公告)号：US20110298102A1

公开(公告)日：2011-12-08

申请号：US12892032

申请日：2010-09-28

申请人： Do-Jae Yoo ,  Young-Do Kweon ,  Joon-Seok Kang ,  Chang-Bae Lee

发明人： Do-Jae Yoo ,  Young-Do Kweon ,  Joon-Seok Kang ,  Chang-Bae Lee

IPC分类号： H01L23/552 ,  H01L21/02

CPC分类号： H01L23/3121 ,  H01L23/49811 ,  H01L23/50 ,  H01L23/552 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73257 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package and a method of manufacturing the semiconductor package are disclosed. A semiconductor package in accordance with an embodiment of the present invention includes a substrate, which is formed with a ground circuit and mounted with a semiconductor chip on one surface, a conductive ground layer, which is formed on the other surface of the substrate and connected with the ground circuit, a molding, which seals up the ground layer and the substrate having the semiconductor chip mounted thereon, and a conductive shield, which covers the molding and is connected with the ground layer. With a semiconductor package in accordance with an embodiment of the present invention, grounding for shielding is possible even in an entirely molded structure, and a double shielding structure to improve the shielding property.

摘要翻译： 公开了一种半导体封装和半导体封装的制造方法。 根据本发明的实施例的半导体封装包括形成有接地电路并且在一个表面上安装有半导体芯片的基板，形成在基板的另一表面上并连接的导电接地层 接地电路，密封接地层和其上安装有半导体芯片的基板的模制件和覆盖模制件并与接地层连接的导电屏蔽件。 利用根据本发明的实施例的半导体封装，即使在完全模制的结构中也可以进行屏蔽的接地，以及用于提高屏蔽性的双重屏蔽结构。

公开(公告)号：US20090244864A1

公开(公告)日：2009-10-01

申请号：US12320794

申请日：2009-02-04

申请人： Woon-Chun Kim ,  Sung Yi ,  Hwa-Sun Park ,  Sang-Chul Lee ,  Jong-Woo Han ,  Young-Do Kweon

发明人： Woon-Chun Kim ,  Sung Yi ,  Hwa-Sun Park ,  Sang-Chul Lee ,  Jong-Woo Han ,  Young-Do Kweon

IPC分类号： H05K1/18 ,  B32B7/00 ,  B32B37/02

CPC分类号： H05K1/162 ,  H05K3/108 ,  H05K3/386 ,  H05K3/387 ,  H05K3/4602 ,  H05K3/4626 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/09672 ,  Y10T428/24355

摘要： Disclosed are a substrate for a capacitor-embedded printed circuit board, a capacitor-embedded printed circuit board, and a manufacturing method thereof. The capacitor-embedded printed circuit board can include a core board, an insulation resin layer, which is stacked on the core board, a first electrode and a first circuit pattern, which are buried in the insulation resin layer, a dielectric layer, which is stacked on a surface of the insulation resin layer, a first adhesive resin layer, which is stacked on the dielectric layer, and a second electrode and a second circuit pattern, which are formed on a surface of the first adhesive resin layer to correspond with the first electrode. With the present invention, the manufacturing process can be simplified and the reliability of products can be improved by reducing the variation of the capacitor (C).

摘要翻译： 公开了用于电容器嵌入式印刷电路板的基板，电容器嵌入式印刷电路板及其制造方法。 电容器嵌入式印刷电路板可以包括堆叠在芯板上的芯板，绝缘树脂层，埋在绝缘树脂层中的第一电极和第一电路图案，介电层，其是 堆叠在绝缘树脂层的表面上，堆叠在电介质层上的第一粘合树脂层和形成在第一粘合树脂层的表面上的第二电极和第二电路图案，以对应于 第一电极。 利用本发明，可以简化制造工艺，并且可以通过减小电容器（C）的变化来提高产品的可靠性。

公开(公告)号：US20120152886A1

公开(公告)日：2012-06-21

申请号：US13403211

申请日：2012-02-23

申请人： Woon-Chun KIM ,  Sung Yi ,  Hwa-Sun Park ,  Sang-Chul Lee ,  Jong-Woo Han ,  Young-Do Kweon

发明人： Woon-Chun KIM ,  Sung Yi ,  Hwa-Sun Park ,  Sang-Chul Lee ,  Jong-Woo Han ,  Young-Do Kweon

IPC分类号： H01G13/00

CPC分类号： H05K1/162 ,  H05K3/108 ,  H05K3/386 ,  H05K3/387 ,  H05K3/4602 ,  H05K3/4626 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/09672 ,  Y10T428/24355

摘要： A method of manufacturing a capacitor-embedded printed circuit board, the method including providing a substrate on which a first metal layer, a dielectric layer and an adhesive resin layer are stacked on the order thereof; etching a part of the first metal layer to form a first electrode and a first circuit pattern; compressing a surface of the substrate, on which the first electrode is formed, onto a core board by interposing an insulation resin layer; forming a second electrode and a second circuit pattern on the adhesive resin layer; stacking an insulation board on the substrate such that the second electrode and the second circuit pattern are covered; and forming a third circuit pattern on the insulation board.

摘要翻译： 一种制造电容器嵌入式印刷电路板的方法，该方法包括提供其上第一金属层，电介质层和粘合树脂层按顺序堆叠的基板; 蚀刻第一金属层的一部分以形成第一电极和第一电路图案; 通过插入绝缘树脂层将形成有第一电极的基板的表面压在芯板上; 在所述粘合树脂层上形成第二电极和第二电路图案; 在所述基板上堆叠绝缘板，使得所述第二电极和所述第二电路图案被覆盖; 以及在所述绝缘板上形成第三电路图案。

公开(公告)号：US08064215B2

公开(公告)日：2011-11-22

申请号：US12230872

申请日：2008-09-05

申请人： Yul-Kyo Chung ,  Sung Yi ,  Soon-Gyu Yim ,  Seog-Moon Choi ,  Jin-Gu Kim ,  Young-Do Kweon

发明人： Yul-Kyo Chung ,  Sung Yi ,  Soon-Gyu Yim ,  Seog-Moon Choi ,  Jin-Gu Kim ,  Young-Do Kweon

IPC分类号： H05K1/18

CPC分类号： H05K1/162 ,  H01L23/3114 ,  H01L23/50 ,  H01L23/5389 ,  H01L23/642 ,  H01L24/25 ,  H01L2224/05001 ,  H01L2224/05548 ,  H01L2224/12105 ,  H01L2224/24227 ,  H01L2224/2518 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19015 ,  H01L2924/19041 ,  H05K1/185 ,  H05K3/4602 ,  H05K2201/09763 ,  H05K2201/10674 ,  H01L2924/00 ,  H01L2224/05599

摘要： A semiconductor chip package and a printed circuit board having an embedded semiconductor chip package are disclosed. The semiconductor chip package may include a semiconductor chip that has at least one chip pad formed on one side, and a capacitor formed on the other side of the semiconductor chip.

摘要翻译： 公开了一种半导体芯片封装和具有嵌入式半导体芯片封装的印刷电路板。 半导体芯片封装可以包括在一侧形成有至少一个芯片焊盘的半导体芯片和形成在半导体芯片的另一侧上的电容器。