公开(公告)号：US08349690B2

公开(公告)日：2013-01-08

申请号：US12649999

申请日：2009-12-30

申请人： Jin-Ku Lee ,  Young-Ho Lee ,  Mi-Ri Lee

发明人： Jin-Ku Lee ,  Young-Ho Lee ,  Mi-Ri Lee

IPC分类号： H01L21/336

CPC分类号： H01L29/7845 ,  H01L21/28518 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10888 ,  H01L29/41791 ,  H01L29/42356 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/7856

摘要： A method for fabricating a semiconductor device includes forming a first conductive layer doped with an impurity for forming a cell junction over a semiconductor substrate, forming a second layer over the first conductive layer, forming a plurality of active regions by etching the second layer and the first conductive layer, the plurality of the active regions being separated from one another by trenches, forming a side contact connected to a sidewall of the first conductive layer, and forming a plurality of metal bit lines each connected to the side contact and filling a portion of each trench.

公开(公告)号：US20110212591A1

公开(公告)日：2011-09-01

申请号：US12964562

申请日：2010-12-09

申请人： Jae-Geun OH ,  Young-Ho Lee ,  Jin-Ku Lee ,  Mi-Ri Lee

发明人： Jae-Geun OH ,  Young-Ho Lee ,  Jin-Ku Lee ,  Mi-Ri Lee

IPC分类号： H01L21/336 ,  H01L21/265

CPC分类号： H01L21/324 ,  H01L21/26513 ,  H01L21/268 ,  H01L21/2686 ,  H01L21/28061 ,  H01L29/66575

摘要： A method for fabricating a transistor of a semiconductor device includes: forming a gate pattern over a substrate; forming a junction region by performing an on implantation process onto the substrate at opposite sides of the gate pattern; performing a solid phase epitaxial (SPE) process on the junction region at a temperature approximately ranging from 770° C. to 850° C.; and performing a rapid thermal annealing (RTA) process on the junction region.

摘要翻译： 一种制造半导体器件的晶体管的方法包括：在衬底上形成栅极图案; 通过在所述栅极图案的相对侧上对所述衬底进行注入工艺来形成结区域; 在大约770℃至850℃的温度下在接合区域进行固相外延（SPE）工艺; 并在接合区域上进行快速热退火（RTA）处理。

公开(公告)号：US20110189843A1

公开(公告)日：2011-08-04

申请号：US12774311

申请日：2010-05-05

申请人： Jin-Ku Lee ,  Jae-Geun Oh ,  Young-Ho Lee ,  Mi-Ri Lee ,  Seung-Beom Baek

发明人： Jin-Ku Lee ,  Jae-Geun Oh ,  Young-Ho Lee ,  Mi-Ri Lee ,  Seung-Beom Baek

IPC分类号： H01L21/306

CPC分类号： H01L29/66575 ,  H01L21/306

摘要： A doping method that forms a doped region at a desired location of a three-dimensional (3D) conductive structure, controls the doping depth and doping dose of the doped region relatively easily, has a shallow doping depth, and prevents a floating body effect. A semiconductor device is fabricated using the same doping method. The method includes, forming a conductive structure having a sidewall, exposing a portion of the sidewall of the conductive structure, and forming a doped region in the exposed portion of the sidewall by performing a plasma doping process.

摘要翻译： 在三维（3D）导电结构的期望位置处形成掺杂区域的掺杂方法相对容易地控制掺杂深度和掺杂区域的掺杂剂量，具有浅掺杂深度，并且防止浮体效应。 使用相同的掺杂方法制造半导体器件。 该方法包括：形成具有侧壁的导电结构，暴露导电结构的侧壁的一部分，以及通过执行等离子体掺杂工艺在侧壁的暴露部分中形成掺杂区域。

公开(公告)号：US20120007258A1

公开(公告)日：2012-01-12

申请号：US12939677

申请日：2010-11-04

申请人： Jae-Geun Oh ,  Seung-Joon Jeon ,  Jin-Ku Lee ,  Mi-Ri Lee ,  Bong-Seok Jeon

发明人： Jae-Geun Oh ,  Seung-Joon Jeon ,  Jin-Ku Lee ,  Mi-Ri Lee ,  Bong-Seok Jeon

IPC分类号： H01L23/522 ,  H01L21/3205

CPC分类号： H01L29/7813 ,  H01L21/743 ,  H01L27/10876 ,  H01L27/10885 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/41741 ,  H01L29/66666 ,  H01L29/7827

摘要： A method for fabricating a semiconductor device includes forming a plurality of bodies that are each isolated from another by a trench and each include a diffusion barrier region with a sidewall exposed to the trench, forming a doped layer gap-filling the trench, forming a sidewall junction at the exposed sidewall of the diffusion barrier region by annealing the doped layer, and forming a conductive line coupled with the sidewall junction to fill the trench.

摘要翻译： 一种制造半导体器件的方法包括：形成多个通过沟槽与另一个隔离的主体，并且每个都包括具有暴露于沟槽的侧壁的扩散阻挡区域，形成填充沟槽的掺杂层间隙，形成侧壁 通过退火掺杂层而在扩散阻挡区域的暴露的侧壁处形成连接，并且形成与侧壁接合部连接以填充沟槽的导电线。

公开(公告)号：US08354342B2

公开(公告)日：2013-01-15

申请号：US12939677

申请日：2010-11-04

申请人： Jae-Geun Oh ,  Seung-Joon Jeon ,  Jin-Ku Lee ,  Mi-Ri Lee ,  Bong-Seok Jeon

发明人： Jae-Geun Oh ,  Seung-Joon Jeon ,  Jin-Ku Lee ,  Mi-Ri Lee ,  Bong-Seok Jeon

IPC分类号： H01L23/522

CPC分类号： H01L29/7813 ,  H01L21/743 ,  H01L27/10876 ,  H01L27/10885 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/41741 ,  H01L29/66666 ,  H01L29/7827

摘要： A method for fabricating a semiconductor device includes forming a plurality of bodies that are each isolated from another by a trench and each include a diffusion barrier region with a sidewall exposed to the trench, forming a doped layer gap-filling the trench, forming a sidewall junction at the exposed sidewall of the diffusion barrier region by annealing the doped layer, and forming a conductive line coupled with the sidewall junction to fill the trench.

摘要翻译： 一种制造半导体器件的方法包括：形成多个通过沟槽与另一个隔离的主体，并且每个都包括具有暴露于沟槽的侧壁的扩散阻挡区域，形成填充沟槽的掺杂层间隙，形成侧壁 通过退火掺杂层而在扩散阻挡区域的暴露的侧壁处形成连接，并且形成与侧壁接合部连接以填充沟槽的导电线。

公开(公告)号：US20120302047A1

公开(公告)日：2012-11-29

申请号：US13230931

申请日：2011-09-13

申请人： Mi-Ri LEE ,  Jae-Geun Oh ,  Seung-Joon Jeon ,  Jin-Ku Lee ,  Bong-Seok Jeon

发明人： Mi-Ri LEE ,  Jae-Geun Oh ,  Seung-Joon Jeon ,  Jin-Ku Lee ,  Bong-Seok Jeon

IPC分类号： H01L21/265

CPC分类号： H01L29/0847 ,  H01L21/26586 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10888 ,  H01L29/66666 ,  H01L29/7827

摘要： A method for fabricating a semiconductor device includes forming a structure having first surfaces at a height above a second surface, which is provided between the first surfaces, forming a first silicon layer on the structure, performing a tilt ion implantation process on the first silicon layer to form a crystalline region and an amorphous region, forming a second silicon layer on the amorphous region, removing the second silicon layer and the first silicon layer until a part of the second surface is exposed, thereby forming an etch barrier, and etching using the etch barrier to form an open part that exposes a part of a sidewall of the structure.

摘要翻译： 一种半导体器件的制造方法，其特征在于，在所述第一面之间形成具有位于第二面以上的高度的第一表面的结构，在所述结构上形成第一硅层，对所述第一硅层进行倾斜离子注入工序 以形成晶体区域和非晶区域，在非晶区域上形成第二硅层，去除第二硅层和第一硅层，直到第二表面的一部分露出，从而形成蚀刻阻挡层，并使用 蚀刻阻挡层以形成暴露结构的侧壁的一部分的开放部分。

公开(公告)号：US07919373B2

公开(公告)日：2011-04-05

申请号：US12165182

申请日：2008-06-30

申请人： Jin-Ku Lee ,  Jae-Geun Oh ,  Sun-Hwan Hwang

发明人： Jin-Ku Lee ,  Jae-Geun Oh ,  Sun-Hwan Hwang

IPC分类号： H01L21/336 ,  H01L21/00 ,  H01L21/20

CPC分类号： H01L21/02667 ,  H01L21/02532 ,  H01L21/02675 ,  H01L27/10876 ,  H01L27/10894

摘要： A method for doping polysilicon improves a doping profile during plasma doping and includes forming a silicon layer using two separate operations. After forming a first silicon layer, thermal annealing is performed to crystallize the first silicon layer, such that the uniformity of a doping concentration according to the depth of a layer inside is improved during plasma doping. Additionally, a doping concentration at the interface between a polysilicon layer and a gate oxide layer is increased. A by-product deposition layer is reduced, which is formed on the surface of a polysilicon layer due to the increase of a doping concentration in a polysilicon layer. As a result, the dopant loss, which is caused by the removing and cleansing of an ion implantation barrier used during doping, is reduced.

摘要翻译： 掺杂多晶硅的方法改善了等离子体掺杂期间的掺杂分布，并且包括使用两个单独的操作形成硅层。 在形成第一硅层之后，进行热退火以使第一硅层结晶，使得在等离子体掺杂期间根据内层的深度的掺杂浓度的均匀性得到改善。 此外，在多晶硅层和栅极氧化物层之间的界面处的掺杂浓度增加。 由于多晶硅层中的掺杂浓度的增加，副产物沉积层被还原，其形成在多晶硅层的表面上。 结果，减少了在掺杂期间使用的离子注入阻挡层的去除和清洁引起的掺杂剂损耗。

公开(公告)号：US20100084720A1

公开(公告)日：2010-04-08

申请号：US12318503

申请日：2008-12-30

申请人： Jae-Geun Oh ,  Jin-Ku Lee ,  Min-Ae Ju

发明人： Jae-Geun Oh ,  Jin-Ku Lee ,  Min-Ae Ju

IPC分类号： H01L29/78 ,  H01L21/425

CPC分类号： H01L29/4916 ,  H01L21/265 ,  H01L21/28035 ,  H01L27/10876 ,  H01L27/10894 ,  H01L29/66621

摘要： A gate of a semiconductor device includes a substrate, and a polysilicon layer over the substrate, wherein the polysilicon layer is doped with first conductive type impurities having a concentration that decreases when receding from the substrate and counter-doped with second conductive type impurities having a concentration that increases when receding from the substrate.

摘要翻译： 半导体器件的栅极包括衬底和衬底上的多晶硅层，其中多晶硅层掺杂有从衬底退出时具有降低的浓度的第一导电型杂质，并与第二导电类型杂质反相掺杂， 从底物后退时增加的浓度。

公开(公告)号：US08063453B2

公开(公告)日：2011-11-22

申请号：US12318503

申请日：2008-12-30

申请人： Jae-Geun Oh ,  Jin-Ku Lee ,  Min-Ae Ju

发明人： Jae-Geun Oh ,  Jin-Ku Lee ,  Min-Ae Ju

IPC分类号： H01L29/78 ,  H01L21/425

CPC分类号： H01L29/4916 ,  H01L21/265 ,  H01L21/28035 ,  H01L27/10876 ,  H01L27/10894 ,  H01L29/66621

摘要： A gate of a semiconductor device includes a substrate, and a polysilicon layer over the substrate, wherein the polysilicon layer is doped with first conductive type impurities having a concentration that decreases when receding from the substrate and counter-doped with second conductive type impurities having a concentration that increases when receding from the substrate.

摘要翻译： 半导体器件的栅极包括衬底和衬底上的多晶硅层，其中多晶硅层掺杂有从衬底退出时具有降低的浓度的第一导电型杂质，并与第二导电类型杂质反相掺杂， 从底物后退时增加的浓度。

公开(公告)号：US07888245B2

公开(公告)日：2011-02-15

申请号：US11743670

申请日：2007-05-03

申请人： Jae-Sung Roh ,  Jae-Geun Oh ,  Hyun-Chul Sohn ,  Sun-Hwan Hwang ,  Jin-Ku Lee

发明人： Jae-Sung Roh ,  Jae-Geun Oh ,  Hyun-Chul Sohn ,  Sun-Hwan Hwang ,  Jin-Ku Lee

IPC分类号： H01L21/20

CPC分类号： H01L21/2236 ,  H01L21/28035

摘要： A plasma doping method includes providing a doping source over a substrate. The doping source includes dopants that are to be injected into the substrate. At least two different bias voltages are applied to inject the dopants from the doping source to the substrate.

摘要翻译： 等离子体掺杂方法包括在衬底上提供掺杂源。 掺杂源包括要注入衬底的掺杂剂。 施加至少两个不同的偏置电压以将掺杂剂从掺杂源注入衬底。