公开(公告)号：US08497555B2

公开(公告)日：2013-07-30

申请号：US13298728

申请日：2011-11-17

申请人： Jin-Gyun Kim ,  Ki-Hyun Hwang ,  Sung-Hae Lee ,  Ji-Hoon Choi

发明人： Jin-Gyun Kim ,  Ki-Hyun Hwang ,  Sung-Hae Lee ,  Ji-Hoon Choi

IPC分类号： H01L29/792 ,  G11C11/40

CPC分类号： H01L29/7926 ,  H01L27/11582 ,  H01L29/1041 ,  H01L29/167 ,  H01L29/7923

摘要： A vertical memory device may include a substrate, a first selection line on the substrate, a plurality of word lines on the first selection line, a second selection line on the plurality of word lines, and a semiconductor channel. The first selection line may be between the plurality of word lines and the substrate, and the plurality of word lines may be between the first and second selection lines. Moreover, the first and second selection lines and the plurality of word lines may be spaced apart in a direction perpendicular with respect to a surface of the substrate. The semiconductor channel may extend away from the surface of the substrate adjacent sidewalls of the first and second selection lines and the plurality of word lines. In addition, portions of the semiconductor channel adjacent the second selection line may be doped with indium and/or gallium. Related methods are also discussed.

摘要翻译： 垂直存储器件可以包括衬底，衬底上的第一选择线，第一选择线上的多个字线，多个字线上的第二选择线，以及半导体沟道。 第一选择线可以在多个字线和衬底之间，并且多个字线可以在第一和第二选择线之间。 此外，第一选择线和第二选择线和多个字线可以在与衬底的表面垂直的方向上间隔开。 半导体通道可以延伸离开衬底的与第一和第二选择线和多个字线的侧壁相邻的表面。 此外，与第二选择线相邻的半导体通道的部分可以掺杂铟和/或镓。 还讨论了相关方法。

公开(公告)号：US20160133643A1

公开(公告)日：2016-05-12

申请号：US14995586

申请日：2016-01-14

申请人： Ji-Hoon Choi ,  Dong-Kyum Kim ,  Jin-Gyun Kim ,  Su-Jin Shin ,  Sang-Hoon Lee ,  Ki-Hyun Hwang

发明人： Ji-Hoon Choi ,  Dong-Kyum Kim ,  Jin-Gyun Kim ,  Su-Jin Shin ,  Sang-Hoon Lee ,  Ki-Hyun Hwang

IPC分类号： H01L27/115 ,  H01L21/28 ,  H01L21/02

CPC分类号： H01L27/11582 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02236 ,  H01L21/02252 ,  H01L21/02255 ,  H01L21/28008 ,  H01L21/28282 ,  H01L27/1157 ,  H01L29/7926

摘要： A semiconductor device is provided. The semiconductor includes a plurality of interlayer insulating layers and a plurality of gate electrodes alternately stacked in a first direction on a substrate. The plurality of interlayer insulating layers and the plurality of gate electrodes constitute a side surface extended in the first direction. A gate dielectric layer is disposed on the side surface. A channel pattern is disposed on the gate dielectric layer. The gate dielectric layer includes a protective pattern, a charge trap layer, and a tunneling layer. The protective pattern includes a portion disposed on a corresponding gate electrode of the plurality of gate electrodes. The charge trap layer is disposed on the protective pattern. The tunneling layer is disposed between the charge trap layer and the channel pattern. The protective pattern is denser than the charge trap layer.

摘要翻译： 提供半导体器件。 半导体包括在基板上沿第一方向交替堆叠的多个层间绝缘层和多个栅电极。 多个层间绝缘层和多个栅电极构成在第一方向上延伸的侧面。 栅电介质层设置在侧表面上。 沟道图案设置在栅介质层上。 栅介质层包括保护图案，电荷陷阱层和隧穿层。 保护图案包括设置在多个栅电极的对应的栅电极上的部分。 电荷陷阱层设置在保护图案上。 隧道层设置在电荷陷阱层和沟道图案之间。 保护图案比电荷陷阱层更致密。

公开(公告)号：US20120267702A1

公开(公告)日：2012-10-25

申请号：US13442482

申请日：2012-04-09

申请人： Jung-Geun JEE ,  Jin-Gyun Kim ,  Jun-Kyu Yang ,  Ji-Hoon Choi ,  Dong-Kyum Kim ,  Ki-Hyun Hwang

发明人： Jung-Geun JEE ,  Jin-Gyun Kim ,  Jun-Kyu Yang ,  Ji-Hoon Choi ,  Dong-Kyum Kim ,  Ki-Hyun Hwang

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L27/11582 ,  H01L27/1157

摘要： A device includes a first GSL, a plurality of first word lines, a first SSL, a plurality of first insulation layer patterns, and a first channel. The first GSL, the first word lines, and the first SSL are spaced apart from each other on a substrate in a first direction perpendicular to a top surface of a substrate. The first insulation layer patterns are between the first GSL, the first word lines and the first SSL. The first channel on the top surface of the substrate extends in the first direction through the first GSL, the first word lines, the first SSL, and the first insulation layer patterns, and has a thickness thinner at a portion thereof adjacent to the first SSL than at portions thereof adjacent to the first insulation layer patterns.

摘要翻译： 一种装置包括第一GSL，多个第一字线，第一SSL，多个第一绝缘层图案和第一通道。 第一GSL，第一字线和第一SSL在垂直于衬底顶表面的第一方向上在衬底上彼此间隔开。 第一绝缘层图案位于第一GSL，第一字线和第一SSL之间。 衬底顶表面上的第一通道沿着第一方向延伸穿过第一GSL，第一字线，第一SSL和第一绝缘层图案，并且在与第一SSL相邻的部分处具有较薄的厚度 而不是靠近第一绝缘层图案的部分。

公开(公告)号：US20140084357A1

公开(公告)日：2014-03-27

申请号：US13949447

申请日：2013-07-24

申请人： Ji-Hoon Choi ,  Dong-Kyum Kim ,  Jin-Gyun Kim ,  Su-Jin Shin ,  Sang-Hoon Lee ,  Ki-Hyun Hwang

发明人： Ji-Hoon Choi ,  Dong-Kyum Kim ,  Jin-Gyun Kim ,  Su-Jin Shin ,  Sang-Hoon Lee ,  Ki-Hyun Hwang

IPC分类号： H01L29/792 ,  H01L21/28

CPC分类号： H01L27/11582 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02236 ,  H01L21/02252 ,  H01L21/02255 ,  H01L21/28008 ,  H01L21/28282 ,  H01L27/1157 ,  H01L29/7926

摘要： A semiconductor device is provided. The semiconductor includes a plurality of interlayer insulating layers and a plurality of gate electrodes alternately stacked in a first direction on a substrate. The plurality of interlayer insulating layers and the plurality of gate electrodes constitute a side surface extended in the first direction. A gate dielectric layer is disposed on the side surface. A channel pattern is disposed on the gate dielectric layer. The gate dielectric layer includes a protective pattern, a charge trap layer, and a tunneling layer. The protective pattern includes a portion disposed on a corresponding gate electrode of the plurality of gate electrodes. The charge trap layer is disposed on the protective pattern. The tunneling layer is disposed between the charge trap layer and the channel pattern. The protective pattern is denser than the charge trap layer.

摘要翻译： 提供半导体器件。 半导体包括在基板上沿第一方向交替堆叠的多个层间绝缘层和多个栅极电极。 多个层间绝缘层和多个栅电极构成在第一方向上延伸的侧面。 栅电介质层设置在侧表面上。 沟道图案设置在栅介质层上。 栅介质层包括保护图案，电荷陷阱层和隧穿层。 保护图案包括设置在多个栅电极的对应的栅电极上的部分。 电荷陷阱层设置在保护图案上。 隧道层设置在电荷陷阱层和沟道图案之间。 保护图案比电荷陷阱层更致密。

公开(公告)号：US09111897B2

公开(公告)日：2015-08-18

申请号：US13716859

申请日：2012-12-17

申请人： Jung-Geun Jee ,  Jin-Gyun Kim ,  Ji-Hoon Choi ,  Ki-Hyun Hwang

发明人： Jung-Geun Jee ,  Jin-Gyun Kim ,  Ji-Hoon Choi ,  Ki-Hyun Hwang

IPC分类号： H01L21/336 ,  H01L21/36 ,  H01L29/66 ,  H01L21/02 ,  H01L27/108 ,  H01L27/115 ,  H01L21/285 ,  H01L21/768 ,  C23C16/24

CPC分类号： H01L21/36 ,  C23C16/24 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02494 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/02595 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/28525 ,  H01L21/28556 ,  H01L21/76876 ,  H01L21/76877 ,  H01L27/10888 ,  H01L27/11582 ,  H01L29/66666

摘要： A method of forming a polysilicon layer includes providing a silicon precursor onto an object loaded in a process chamber to form a seed layer. The silicon precursor includes a nitrogen containing silicon precursor and a chlorine containing silicon precursor. The method further includes providing a silicon source on the seed layer.

摘要翻译： 形成多晶硅层的方法包括将硅前体提供到加载在处理室中的物体上以形成种子层。 硅前体包括含氮的硅前体和含氯的硅前体。 该方法还包括在种子层上提供硅源。

公开(公告)号：US08815676B2

公开(公告)日：2014-08-26

申请号：US13671948

申请日：2012-11-08

申请人： Sang-Ryol Yang ,  Yoo-Chul Kong ,  Jung-Ho Kim ,  Jin-Gyun Kim ,  Jae-Jin Shin ,  Ji-Hoon Choi

发明人： Sang-Ryol Yang ,  Yoo-Chul Kong ,  Jung-Ho Kim ,  Jin-Gyun Kim ,  Jae-Jin Shin ,  Ji-Hoon Choi

IPC分类号： H01L21/00

CPC分类号： H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157

摘要： Methods of forming vertical nonvolatile memory devices may include forming an electrically insulating layer, which includes a composite of a sacrificial layer sandwiched between first and second mold layers. An opening extends through the electrically insulating layer and exposes inner sidewalls of the first and second mold layers and the sacrificial layer. A sidewall of the opening may be lined with an electrically insulating protective layer and a first semiconductor layer may be formed on an inner sidewall of the electrically insulating protective layer within the opening. At least a portion of the sacrificial layer may then be selectively etched from between the first and second mold layers to thereby define a lateral recess therein, which exposes an outer sidewall of the electrically insulating protective layer.

摘要翻译： 形成垂直非易失性存储器件的方法可以包括形成电绝缘层，其包括夹在第一和第二模具层之间的牺牲层的复合材料。 开口延伸穿过电绝缘层并暴露第一和第二模具层和牺牲层的内侧壁。 开口的侧壁可以衬有电绝缘保护层，并且可以在开口内的电绝缘保护层的内侧壁上形成第一半导体层。 然后可以从第一和第二模具层之间选择性地蚀刻牺牲层的至少一部分，从而在其中限定其中暴露电绝缘保护层的外侧壁的横向凹部。

公开(公告)号：US20130065369A1

公开(公告)日：2013-03-14

申请号：US13671948

申请日：2012-11-08

申请人： Sang-Ryol Yang ,  Yoo-Chul Kong ,  Jung-Ho Kim ,  Jin-Gyun Kim ,  Jae-Jin Shin ,  Ji-Hoon Choi

发明人： Sang-Ryol Yang ,  Yoo-Chul Kong ,  Jung-Ho Kim ,  Jin-Gyun Kim ,  Jae-Jin Shin ,  Ji-Hoon Choi

IPC分类号： H01L21/336

CPC分类号： H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157

摘要： Methods of forming vertical nonvolatile memory devices may include forming an electrically insulating layer, which includes a composite of a sacrificial layer sandwiched between first and second mold layers. An opening extends through the electrically insulating layer and exposes inner sidewalls of the first and second mold layers and the sacrificial layer. A sidewall of the opening may be lined with an electrically insulating protective layer and a first semiconductor layer may be formed on an inner sidewall of the electrically insulating protective layer within the opening. At least a portion of the sacrificial layer may then be selectively etched from between the first and second mold layers to thereby define a lateral recess therein, which exposes an outer sidewall of the electrically insulating protective layer.

摘要翻译： 形成垂直非易失性存储器件的方法可以包括形成电绝缘层，其包括夹在第一和第二模具层之间的牺牲层的复合材料。 开口延伸穿过电绝缘层并暴露第一和第二模具层和牺牲层的内侧壁。 开口的侧壁可以衬有电绝缘保护层，并且可以在开口内的电绝缘保护层的内侧壁上形成第一半导体层。 然后可以从第一和第二模具层之间选择性地蚀刻牺牲层的至少一部分，从而在其中限定其中暴露电绝缘保护层的外侧壁的横向凹部。

公开(公告)号：US20120083077A1

公开(公告)日：2012-04-05

申请号：US13228433

申请日：2011-09-08

申请人： Sang-Ryol Yang ,  Yoo-Chul Kong ,  Jin-Gyun Kim ,  Jae-Jin Shin ,  Jung-Ho Kim ,  Ji-Hoon Choi

发明人： Sang-Ryol Yang ,  Yoo-Chul Kong ,  Jin-Gyun Kim ,  Jae-Jin Shin ,  Jung-Ho Kim ,  Ji-Hoon Choi

IPC分类号： H01L21/336 ,  H01L21/28

CPC分类号： H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157

摘要： Methods of forming vertical nonvolatile memory devices may include forming an electrically insulating layer, which includes a composite of a sacrificial layer sandwiched between first and second mold layers. An opening extends through the electrically insulating layer and exposes inner sidewalls of the first and second mold layers and the sacrificial layer. A sidewall of the opening may be lined with an electrically insulating protective layer and a first semiconductor layer may be formed on an inner sidewall of the electrically insulating protective layer within the opening. At least a portion of the sacrificial layer may then be selectively etched from between the first and second mold layers to thereby define a lateral recess therein, which exposes an outer sidewall of the electrically insulating protective layer.

摘要翻译： 形成垂直非易失性存储器件的方法可以包括形成电绝缘层，其包括夹在第一和第二模具层之间的牺牲层的复合材料。 开口延伸穿过电绝缘层并暴露第一和第二模具层和牺牲层的内侧壁。 开口的侧壁可以衬有电绝缘保护层，并且可以在开口内的电绝缘保护层的内侧壁上形成第一半导体层。 然后可以从第一和第二模具层之间选择性地蚀刻牺牲层的至少一部分，从而在其中限定其中暴露电绝缘保护层的外侧壁的横向凹部。

公开(公告)号：US08309405B2

公开(公告)日：2012-11-13

申请号：US13228433

申请日：2011-09-08

申请人： Sang-Ryol Yang ,  Yoo-Chul Kong ,  Jin-Gyun Kim ,  Jae-Jin Shin ,  Jung-Ho Kim ,  Ji-Hoon Choi

发明人： Sang-Ryol Yang ,  Yoo-Chul Kong ,  Jin-Gyun Kim ,  Jae-Jin Shin ,  Jung-Ho Kim ,  Ji-Hoon Choi

IPC分类号： H01L21/3205 ,  H01L21/4763 ,  H01L21/44

CPC分类号： H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157

摘要： Methods of forming vertical nonvolatile memory devices may include forming an electrically insulating layer, which includes a composite of a sacrificial layer sandwiched between first and second mold layers. An opening extends through the electrically insulating layer and exposes inner sidewalls of the first and second mold layers and the sacrificial layer. A sidewall of the opening may be lined with an electrically insulating protective layer and a first semiconductor layer may be formed on an inner sidewall of the electrically insulating protective layer within the opening. At least a portion of the sacrificial layer may then be selectively etched from between the first and second mold layers to thereby define a lateral recess therein, which exposes an outer sidewall of the electrically insulating protective layer.

摘要翻译： 形成垂直非易失性存储器件的方法可以包括形成电绝缘层，其包括夹在第一和第二模具层之间的牺牲层的复合材料。 开口延伸穿过电绝缘层并暴露第一和第二模具层和牺牲层的内侧壁。 开口的侧壁可以衬有电绝缘保护层，并且可以在开口内的电绝缘保护层的内侧壁上形成第一半导体层。 然后可以从第一和第二模具层之间选择性地蚀刻牺牲层的至少一部分，从而在其中限定其中暴露电绝缘保护层的外侧壁的横向凹部。

公开(公告)号：US07983647B2

公开(公告)日：2011-07-19

申请号：US12012383

申请日：2008-01-31

申请人： Ji-Hoon Choi ,  Sung-Kwon Jo

发明人： Ji-Hoon Choi ,  Sung-Kwon Jo

IPC分类号： H04B1/10

CPC分类号： H04B1/7107 ,  H04B1/71075 ,  H04B2201/70701

摘要： A method for determining a scaling factor in a communication system. The method includes calculating an average power for each of an input signal and an output signal of a channel predictor; calculating a noise variance using the calculated average power; normalizing the noise variance with an average power of the channel predictor's output signal; and determining a scaling factor using the normalized noise variance.

摘要翻译： 一种用于确定通信系统中的缩放因子的方法。 该方法包括计算信道预测器的输入信号和输出信号中的每一者的平均功率; 使用计算的平均功率计算噪声方差; 利用信道预测器的输出信号的平均功率来规范噪声方差; 以及使用所述归一化噪声方差来确定缩放因子。