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    Semiconductor hybrid component
    1.
    发明授权
    Semiconductor hybrid component 失效
    半导体混合元件

    公开(公告)号：US5726500A

    公开(公告)日：1998-03-10

    申请号：US549812

    申请日：1995-12-07

    Applicant: Jean-Yves Duboz ,  Emmanuel Rosencher ,  Philippe Bois

    Inventor： Jean-Yves Duboz ,  Emmanuel Rosencher ,  Philippe Bois

    IPC: H01L27/146 ,  H01L23/48 ,  H01L23/50 ,  H01L29/44

    CPC classification number: H01L27/1465 ,  H01L2224/48091 ,  H01L2224/48463 ,  H01L2924/10253

    Abstract: Semiconductor hybrid components, especially linear infrared detectors produced by hybridization. A main substrate has integrated thereon active elements which cannot be produced on a silicon substrate. The substrate is made, for example, of AsGa, InP, HgCdTe or PbTe. Several silicon chips are mounted on the main substrate, by hybridization using indium balls. These chips include the read and multiplexing circuits. The silicon chips remain of limited size (a few millimeters) so that the differential thermal expansion stresses are limited, but the detection array may be produced as one piece without butt-joining. It is therefore possible to produce arrays of great length (several centimeters) and of high resolution (at least a thousand points).

    Abstract translation: PCT No.PCT / FR95 / 00448第 371 1995年12月7日第 102（e）日期1995年12月7日PCT提交1995年4月7日PCT公布。 公开号WO95 / 28006 日期1995年10月19日半导体混合元件，特别是通过杂交产生的线性红外探测器。 主衬底上集成有不能在硅衬底上产生的有源元件。 衬底例如由AsGa，InP，HgCdTe或PbTe制成。 通过使用铟球杂交，将几个硅芯片安装在主基板上。 这些芯片包括读和多路复用电路。 硅芯片保持有限的尺寸（几毫米），使得差分热膨胀应力受到限制，但是检测阵列可以制成一体而不具有对接。 因此，可以生产长度（几厘米）和高分辨率（至少一千点）的阵列。

    Integrated direction finder
    2.
    发明授权
    Integrated direction finder 失效
    集成式取向器

    公开(公告)号：US5719670A

    公开(公告)日：1998-02-17

    申请号：US555323

    申请日：1995-11-08

    Applicant: Jean-Yves Duboz ,  Philippe Bois

    Inventor： Jean-Yves Duboz ,  Philippe Bois

    IPC: G01S3/784 ,  G01B11/26

    CPC classification number: G01S3/784

    Abstract: Disclosed is an integrated direction finder that can be used to determine the direction of a light beam and, in particular, a laser beam. This direction finder has a substrate transparent to the light beam and means on the rear face to channel a part of the light flux received on this face to the front face which has several photodetector elements. Application to optical measurements.

    Abstract translation: 公开了一种可用于确定光束的方向，特别是激光束的集成测向器。 该测向器具有对光束透明的基板和背面上的装置，以将接收在该表面上的光通量的一部分引导到具有若干光电检测器元件的正面。 应用于光学测量。

    Large photodetector array
    3.
    发明授权
    Large photodetector array 失效
    大型光电探测器阵列

    公开(公告)号：US5712499A

    公开(公告)日：1998-01-27

    申请号：US555079

    申请日：1995-11-08

    Applicant: Jean-Yves Duboz ,  Philippe Bois

    Inventor： Jean-Yves Duboz ,  Philippe Bois

    IPC: H01L27/146 ,  H01L31/062 ,  H01L31/113 ,  H01L31/00

    CPC classification number: H01L27/14643

    Abstract: A photodetector arrangement capable of detecting high-power-light flux and including a set of elementary photodetectors each one of which is individually tested to determine that it has no defects. Each of the photodetectors which is found to be free of objectionable defects is connected in parallel to a common conducting line to thus produce a combined output when radiation impinges on the detector surface. The connection can be hard wired or provided through a set of transistors acting as connection control intermediaries between the good photodetectors and the common conducting line. The active areas of only good photodetectors are thus combined to form a large photodetector area of any desired shape or size without the usual reliability problems. The selective control of the transistors can further be provided by auxiliary control photodetectors to additionally automatically control the size of the active area in response to the area of light being detected or a control light beam.

    Abstract translation: 一种能够检测高功率光通量并且包括一组基本光电检测器的光电检测器装置，其中每一个被单独测试以确定其没有缺陷。 发现没有令人反感的缺陷的每个光电检测器与公共导线并联连接，从而当辐射照射在检测器表面上时产生组合的输出。 连接可以通过一组晶体管进行硬连线或提供，这些晶体管充当良好光电检测器和公共导线之间的连接控制中介。 因此，只有良好的光电检测器的有效区域被组合以形成任何期望的形状或尺寸的大的光电检测器区域，而没有通常的可靠性问题。 晶体管的选择性控制可以由辅助控制光电探测器进一步提供，以响应于正被检测的光的面积或控制光束另外自动控制有效面积的大小。

    PROCESS FOR INTEGRATNG A III-N TYPE COMPONENT ON A (001) NOMINAL SILICIUM SUBSTRATE
    5.
    发明申请
    PROCESS FOR INTEGRATNG A III-N TYPE COMPONENT ON A (001) NOMINAL SILICIUM SUBSTRATE 有权
    在（001）名称硅基底上形成III-N型组分的方法

    公开(公告)号：US20080149936A1

    公开(公告)日：2008-06-26

    申请号：US11941590

    申请日：2007-11-16

    Applicant: SYLVAIN JOBLOT ,  Fabrice Semond ,  Jean Massies ,  Yvon Cordier ,  Jean-Yves Duboz

    Inventor： SYLVAIN JOBLOT ,  Fabrice Semond ,  Jean Massies ,  Yvon Cordier ,  Jean-Yves Duboz

    IPC: H01L21/763 ,  H01L31/0368

    CPC classification number: H01L21/02658 ,  C30B23/025 ,  C30B23/04 ,  C30B25/04 ,  C30B25/183 ,  C30B29/406 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02639 ,  H01L21/02664 ,  H01L27/0605 ,  H01L29/2003 ,  H01L33/007

    Abstract: A process is provided for integrating a III-N component, such as GaN, on a (001) or (100) nominal silicon substrate. There are arranged a texture of elementary areas each comprising an individual surface, with the texture comprising at least one hosting area intended to receive a III-N component. A mask layer is deposited on non-hosting areas which are not intended to receive a III-N type component. The hosting area is locally prepared so as to generate on the surface of the area one domain comprising one single type of terrace. There is grown by Molecular Beam Epitaxy or Metalorganic Vapor Phase Epitaxy on the hosting area one intermediary AlN buffer layer, followed by the growth of one III-N based material so as to realize a substantially monocrystalline structure. There is eliminated the mask layer located on non-hosting areas as well as surface polycrystalline layers deposited above the mask layers, and MOS/CMOS structures are subsequent integrated on at least some of the non-hosting areas.

    Abstract translation: 提供了在（001）或（100）标称硅衬底上将诸如GaN的III-N成分整合的工艺。 布置了各自包括单独表面的基本区域的纹理，其中纹理包括用于接收III-N分量的至少一个托管区域。 掩模层沉积在不意图接收III-N型组件的非托管区域上。 托管区域是本地准备的，以便在该区域的表面上生成包括一个单一类型的露台的一个域。 通过分子束外延或金属有机气相外延生长在托管区域一个中间AlN缓冲层，随后生长一种III-N基材料，以实现基本上单晶结构。 消除了位于非托管区域上的掩模层以及沉积在掩模层上方的表面多晶层，随后将MOS / CMOS结构集成在至少一些非托管区域上。

    Process for integrating a III-N type component on a (001) nominal silicium substrate
    6.
    发明授权
    Process for integrating a III-N type component on a (001) nominal silicium substrate 有权
    在（001）标称硅衬底上集成III-N型组分的方法

    公开(公告)号：US07785991B2

    公开(公告)日：2010-08-31

    申请号：US11941590

    申请日：2007-11-16

    Applicant: Sylvain Joblot ,  Fabrice Semond ,  Jean Massies ,  Yvon Cordier ,  Jean-Yves Duboz

    Inventor： Sylvain Joblot ,  Fabrice Semond ,  Jean Massies ,  Yvon Cordier ,  Jean-Yves Duboz

    IPC: H01L21/20

    CPC classification number: H01L21/02658 ,  C30B23/025 ,  C30B23/04 ,  C30B25/04 ,  C30B25/183 ,  C30B29/406 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02639 ,  H01L21/02664 ,  H01L27/0605 ,  H01L29/2003 ,  H01L33/007

    Abstract: A process is provided for integrating a III-N component, such as GaN, on a (001) or (100) nominal silicon substrate. There are arranged a texture of elementary areas each comprising an individual surface, with the texture comprising at least one hosting area intended to receive a III-N component. A mask layer is deposited on non-hosting areas which are not intended to receive a III-N type component. The hosting area is locally prepared so as to generate on the surface of the area one domain comprising one single type of terrace. There is grown by Molecular Beam Epitaxy or Metalorganic Vapor Phase Epitaxy on the hosting area one intermediary AlN buffer layer, followed by the growth of one III-N based material so as to realize a substantially monocrystalline structure. There is eliminated the mask layer located on non-hosting areas as well as surface polycrystalline layers deposited above the mask layers, and MOS/CMOS structures are subsequent integrated on at least some of the non-hosting areas.

    Abstract translation: 提供了在（001）或（100）标称硅衬底上将诸如GaN的III-N成分整合的工艺。 布置了各自包括单独表面的基本区域的纹理，其中纹理包括用于接收III-N分量的至少一个托管区域。 掩模层沉积在不意图接收III-N型组件的非托管区域上。 托管区域是本地准备的，以便在该区域的表面上生成包括一个单一类型的露台的一个域。 通过分子束外延或金属有机气相外延生长在托管区域一个中间AlN缓冲层，随后生长一种III-N基材料，以实现基本上单晶结构。 消除了位于非托管区域上的掩模层以及沉积在掩模层上方的表面多晶层，随后将MOS / CMOS结构集成在至少一些非托管区域上。

    Optical detection device with variable detection threshold
    7.
    发明授权
    Optical detection device with variable detection threshold 失效
    具有可变检测阈值的光学检测装置

    公开(公告)号：US5140381A

    公开(公告)日：1992-08-18

    申请号：US672553

    申请日：1991-03-20

    Applicant: Pierre A. Badoz ,  Jean-Yves Duboz

    Inventor： Pierre A. Badoz ,  Jean-Yves Duboz

    IPC: G01J1/02 ,  H01L31/101 ,  H01L31/108

    CPC classification number: H01L31/108 ,  H01L31/101

    Abstract: An optical detection device with a variable detection threshold. The optical detection device comprises at least one element having a heterostructure on a substrate, the heterostructure incorporating two conducting layers and, between the latter, a semiconducting layer forming a potential barrier with each of the conducting layers is provided. Excited electrons are formed when the heterostructure is illuminated by light radiation, whose energy is at least equal to the detection threshold of the heterostructure. This makes it possible to detect the radiation by an internal photoemission of electrons between one conducting layer and the other. The device also comprises variable biasing of the heterostructure, the biasing making it possible to vary the detection spectrum and threshold of the device. The optical detection device finds particular application to the detection of infrared radiation.

    Abstract translation: 具有可变检测阈值的光学检测装置。 光学检测装置包括至少一个在衬底上具有异质结构的元件，所述异质结构包含两个导电层，并且在其间形成与每个导电层形成势垒的半导体层。 当异质结构被能量至少等于异质结构的检测阈值的光辐射照射时，形成激发电子。 这使得可以通过在一个导电层和另一个之间的电子的内部发光来检测辐射。 该器件还包括异质结构的可变偏置，偏置使得可以改变器件的检测光谱和阈值。 光学检测装置特别适用于红外辐射的检测。

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