公开(公告)号：US08995166B2

公开(公告)日：2015-03-31

申请号：US13721279

申请日：2012-12-20

Applicant: Intermolecular Inc. ,  Kabushiki Kaisha Toshiba ,  SanDisk 3D LLC

Inventor： Dipankar Pramanik ,  David E Lazovsky ,  Tim Minvielle ,  Takeshi Yamaguchi

IPC: G11C11/00 ,  G11C13/00 ,  G11C11/56 ,  H01L45/00 ,  H01L27/24

CPC classification number: G11C11/56 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/1078 ,  G11C7/12 ,  G11C7/22 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/004 ,  G11C13/0069 ,  G11C2213/32 ,  G11C2213/33 ,  G11C2213/34 ,  G11C2213/72 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2481 ,  H01L45/145 ,  H01L45/1608

Abstract: A resistor array for multi-bit data storage without the need to increase the size of a memory chip or scale down the feature size of a memory cell contained within the memory chip is provided. The resistor array incorporates a number of discrete resistive elements to be selectively connected, in different series combinations, to at least one memory cell or memory device. In one configuration, by connecting each memory cell or device with at least one resistor array, a resistive switching layer found in the resistive switching memory element of the connected memory device is capable of being at multiple resistance states for storing multiple bits of digital information. During device programming operations, when a desired series combination of the resistive elements within the resistor array is selected, the resistive switching layer in the connected memory device can be in a desired resistance state.

Abstract translation: 提供了用于多位数据存储的电阻器阵列，而不需要增加存储器芯片的尺寸或缩小存储器芯片中包含的存储器单元的特征尺寸。 电阻器阵列包括多个离散电阻元件，以便以不同的串联组合方式连接到至少一个存储器单元或存储器件。 在一种配置中，通过将每个存储器单元或设备连接至少一个电阻器阵列，在连接的存储器件的电阻式开关存储器元件中发现的电阻式开关层能够处于多个电阻状态，用于存储多位数字信息。 在器件编程操作期间，当选择电阻器阵列内的电阻元件的期望的串联组合时，连接的存储器件中的电阻式开关层可以处于期望的电阻状态。

公开(公告)号：US09331279B2

公开(公告)日：2016-05-03

申请号：US14702374

申请日：2015-05-01

Applicant: Intermolecular Inc.

Inventor： Dipankar Pramanik ,  Tony P. Chiang ,  David E Lazovsky

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1658 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1683

Abstract: An embodiment of the present invention sets forth an embedded resistive memory cell that includes a first stack of deposited layers, a second stack of deposited layers, a first electrode disposed under a first portion of the first stack, and a second electrode disposed under a second portion of the first stack and extending from under the second portion of the first stack to under the second stack. The second electrode is disposed proximate to the first electrode within the embedded resistive memory cell. The first stack of deposited layers includes a dielectric layer, a high-k dielectric layer disposed above the dielectric layer, and a metal layer disposed above the high-k dielectric layer. The second stack of deposited layers includes a high-k dielectric layer formed simultaneously with the high-k dielectric layer included in the first stack, and a metal layer disposed above the high-k dielectric layer.

公开(公告)号：US09362231B2

公开(公告)日：2016-06-07

申请号：US14885002

申请日：2015-10-16

Applicant: Intermolecular Inc.

Inventor： Tony P. Chiang ,  Majid Keshavarz ,  David E Lazovsky

IPC: H01L21/768 ,  H01L23/532 ,  B82Y30/00 ,  H01L21/31 ,  H01L29/06 ,  H01L49/02

CPC classification number: H01L23/5329 ,  B82Y30/00 ,  H01L21/31 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76873 ,  H01L21/76879 ,  H01L28/65 ,  H01L29/06 ,  H01L2924/0002 ,  Y10T428/249953 ,  H01L2924/00

Abstract: Methods for sealing a porous dielectric are presented including: receiving a substrate, the substrate including the porous dielectric; exposing the substrate to an organosilane, where the organosilane includes a hydrolysable group for facilitating attachment with the porous dielectric, and where the organosilane does not include an alkyl group; and forming a layer as a result of the exposing to seal the porous dielectric. In some embodiments, methods are presented where the organosilane includes: alkynyl groups, aryl groups, fluoroalkyl groups, heteroaryl groups, alcohol groups, thiol groups, amine groups, thiocarbamate groups, ester groups, ether groups, sulfide groups, and nitrile groups. In some embodiments, method further include: removing contamination from the porous dielectric and a conductive region of the substrate prior to the exposing; and removing contamination from the conductive region after the forming.

公开(公告)号：US09275727B2

公开(公告)日：2016-03-01

申请号：US14627760

申请日：2015-02-20

Applicant: Intermolecular Inc. ,  Kabushiki Kaisha Toshiba ,  SanDisk 3D LLC

Inventor： Dipankar Pramanik ,  David E Lazovsky ,  Tim Minvielle ,  Takeshi Yamaguchi

IPC: G11C11/00 ,  G11C11/56 ,  G11C13/00 ,  G11C7/10 ,  G11C7/22 ,  G11C7/12 ,  H01L45/00 ,  H01L27/24

CPC classification number: G11C11/56 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/1078 ,  G11C7/12 ,  G11C7/22 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/004 ,  G11C13/0069 ,  G11C2213/32 ,  G11C2213/33 ,  G11C2213/34 ,  G11C2213/72 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2481 ,  H01L45/145 ,  H01L45/1608

Abstract: A resistor array for multi-bit data storage without the need to increase the size of a memory chip or scale down the feature size of a memory cell contained within the memory chip is provided. The resistor array incorporates a number of discrete resistive elements to be selectively connected, in different series combinations, to at least one memory cell or memory device. In one configuration, by connecting each memory cell or device with at least one resistor array, a resistive switching layer found in the resistive switching memory element of the connected memory device is capable of being at multiple resistance states for storing multiple bits of digital information. During device programming operations, when a desired series combination of the resistive elements within the resistor array is selected, the resistive switching layer in the connected memory device can be in a desired resistance state.

公开(公告)号：US09054032B2

公开(公告)日：2015-06-09

申请号：US14325580

申请日：2014-07-08

Applicant: Intermolecular Inc.

Inventor： Dipankar Pramanik ,  Tony P. Chiang ,  David E Lazovsky

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L45/1658 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1683

Abstract: An embodiment of the present invention sets forth an embedded resistive memory cell that includes a first stack of deposited layers, a second stack of deposited layers, a first electrode disposed under a first portion of the first stack, and a second electrode disposed under a second portion of the first stack and extending from under the second portion of the first stack to under the second stack. The second electrode is disposed proximate to the first electrode within the embedded resistive memory cell. The first stack of deposited layers includes a dielectric layer, a high-k dielectric layer disposed above the dielectric layer, and a metal layer disposed above the high-k dielectric layer. The second stack of deposited layers includes a high-k dielectric layer formed simultaneously with the high-k dielectric layer included in the first stack, and a metal layer disposed above the high-k dielectric layer.

Abstract translation: 本发明的实施例提出了一种嵌入式电阻式存储单元，其包括沉积层的第一堆叠，沉积层的第二堆叠，设置在第一堆叠的第一部分下方的第一电极和设置在第二堆叠下的第二电极的第二电极 第一堆叠的部分并且从第一堆叠的第二部分下方延伸到第二堆叠下方。 第二电极设置在嵌入式电阻式存储单元内靠近第一电极。 第一堆沉积层包括介电层，设置在电介质层上方的高k电介质层和设置在高k电介质层上方的金属层。 第二层沉积层包括与包含在第一堆叠中的高k电介质层同时形成的高k电介质层，以及设置在高k电介质层上方的金属层。

公开(公告)号：US20140319449A1

公开(公告)日：2014-10-30

申请号：US14325580

申请日：2014-07-08

Applicant: Intermolecular Inc.

Inventor： Dipankar Pramanik ,  Tony P. Chiang ,  David E Lazovsky

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L45/1658 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1683

Abstract: An embodiment of the present invention sets forth an embedded resistive memory cell that includes a first stack of deposited layers, a second stack of deposited layers, a first electrode disposed under a first portion of the first stack, and a second electrode disposed under a second portion of the first stack and extending from under the second portion of the first stack to under the second stack. The second electrode is disposed proximate to the first electrode within the embedded resistive memory cell. The first stack of deposited layers includes a dielectric layer, a high-k dielectric layer disposed above the dielectric layer, and a metal layer disposed above the high-k dielectric layer. The second stack of deposited layers includes a high-k dielectric layer formed simultaneously with the high-k dielectric layer included in the first stack, and a metal layer disposed above the high-k dielectric layer.

Abstract translation: 本发明的实施例提出了一种嵌入式电阻式存储单元，其包括沉积层的第一堆叠，沉积层的第二堆叠，设置在第一堆叠的第一部分下方的第一电极和设置在第二堆叠下的第二电极的第二电极 第一堆叠的部分并且从第一堆叠的第二部分下方延伸到第二堆叠下方。 第二电极设置在嵌入式电阻式存储单元内靠近第一电极。 第一堆沉积层包括介电层，设置在电介质层上方的高k电介质层和设置在高k电介质层上方的金属层。 第二层沉积层包括与包含在第一堆叠中的高k电介质层同时形成的高k电介质层和设置在高k电介质层上方的金属层。