知搜-全球专利检索

  1. 登录
  2. 注册

搜索结果

38 条记录 (耗时 0.018 秒)

    Configurable write command delay in nonvolatile memory
    1.
    发明授权
    Configurable write command delay in nonvolatile memory 有权

    公开(公告)号：US11188264B2

    公开(公告)日：2021-11-30

    申请号：US16780632

    申请日：2020-02-03

    申请人： Intel Corporation

    发明人： Shekoufeh Qawami ,  Philip Hillier ,  Benjamin Graniello ,  Rajesh Sundaram

    IPC分类号： G06F3/06

    摘要： A memory system includes a nonvolatile (NV) memory device with asymmetry between intrinsic read operation delay and intrinsic write operation delay. The system can select to perform memory access operations with the NV memory device with the asymmetry, in which case write operations have a lower delay than read operations. The system can alternatively select to perform memory access operations with the NV memory device where a configured write operation delay that matches the read operation delay.

    COMPUTER-ASSISTED OR AUTONOMOUS DRIVING VEHICLE INCIDENT MANAGEMENT METHOD AND APPARATUS
    4.
    发明申请
    COMPUTER-ASSISTED OR AUTONOMOUS DRIVING VEHICLE INCIDENT MANAGEMENT METHOD AND APPARATUS 审中-公开

    公开(公告)号：US20190049969A1

    公开(公告)日：2019-02-14

    申请号：US16118206

    申请日：2018-08-30

    申请人： Intel Corporation

    发明人： Shekoufeh Qawami ,  Casey Baron ,  Kooi Chi Ooi ,  Naissa Conde ,  Mengjie Yu

    IPC分类号： G05D1/00 ,  G07C5/08 ,  G05D1/02 ,  G07C5/00

    摘要： Apparatuses, methods and storage medium associated with computer-assisted or autonomous vehicle incident management, are disclosed herein. In some embodiments, a vehicle incident management system includes a main system controller to determine whether a vehicle hosting the apparatus is involved in a vehicle incident; if so, whether another vehicle is involved; and if so, whether the other vehicle is equipped to exchange incident information; and an inter-vehicle communication subsystem to exchange incident information with the other vehicle, on determination that the vehicle is involved in a vehicle incident involving the other vehicle, and the other vehicle is equipped to exchange incident information. Other embodiments are also described and claimed.

    METHODS, SYSTEMS, ARTICLES OF MANUFACTURE AND APPARATUS TO IMPROVE BOUNDARY EXCURSION DETECTION
    5.
    发明申请
    METHODS, SYSTEMS, ARTICLES OF MANUFACTURE AND APPARATUS TO IMPROVE BOUNDARY EXCURSION DETECTION 审中-公开

    公开(公告)号：US20190049933A1

    公开(公告)日：2019-02-14

    申请号：US16144840

    申请日：2018-09-27

    申请人： Intel Corporation

    发明人： Shekoufeh Qawami ,  Chaitanya Sreerama ,  Hassnaa Moustafa ,  Rita Wouhaybi ,  Nadine L. Dabby

    IPC分类号： G05B19/418 ,  G05B13/04

    摘要： Methods, apparatus, systems and articles of manufacture are disclosed to improve boundary excursion detection. An example apparatus to improve boundary excursion detection includes a metadata extractor to parse a first control stream to extract embedded metadata, a metadata label resolver to classify a boundary term of the extracted embedded metadata, a candidate stream selector to identify candidate second control streams that include a boundary term that matches the classified boundary term of the first control stream, and a boundary vector calculator to improve boundary excursion detection by calculating a boundary vector factor based on respective ones of the candidate second control streams that include the classified boundary term.

    Auto-increment write count for nonvolatile memory
    6.
    发明授权
    Auto-increment write count for nonvolatile memory 有权

    公开(公告)号：US11200113B2

    公开(公告)日：2021-12-14

    申请号：US16742332

    申请日：2020-01-14

    申请人： Intel Corporation

    发明人： Shekoufeh Qawami

    IPC分类号： G06F11/10 ,  G06F11/07 ,  G06F3/06 ,  G06F9/54 ,  G06F9/30

    摘要： A memory device has multiple nonvolatile (NV) memory arrays that collectively store a block of data, with each array to store a portion of the data block. A selected NV memory array stores a write count for the block of data. In response to a write command, the NV memory arrays that store data perform an internal pre-write read. The selected NV memory array that stores the write count will perform a pre-write read of the write count, increment the write count internally to the selected NV memory array, and write the incremented write count back to the selected NV memory array.

    Interface for storage device access over memory bus
    8.
    发明授权
    Interface for storage device access over memory bus 有权
    通过存储器总线访问存储设备的接口

    公开(公告)号：US09064560B2

    公开(公告)日：2015-06-23

    申请号：US14075765

    申请日：2013-11-08

    申请人： Intel Corporation

    发明人： Shekoufeh Qawami ,  Rajesh Sundaram ,  David J. Zimmerman ,  Robert W. Faber

    IPC分类号： G06F1/12 ,  G06F13/42 ,  H04L5/00 ,  H04L7/00 ,  G06F13/16 ,  G11C7/22

    CPC分类号： G06F13/28 ,  G06F1/12 ,  G06F12/0246 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/385 ,  G06F13/409 ,  G06F13/42 ,  G06F2212/7201 ,  G06F2212/7203 ,  G11C7/222 ,  H04L5/00 ,  H04L7/00 ,  Y02D10/14 ,  Y02D10/151

    摘要： A nonvolatile storage or memory device is accessed over a memory bus. The memory bus has an electrical interface typically used for volatile memory devices. A controller coupled to the bus sends synchronous data access commands to the nonvolatile memory device, and reads the response from the device bus based on an expected timing of a reply from the nonvolatile memory device. The controller determines the expected timing based on when the command was sent, and characteristics of the nonvolatile memory device. The controller may not need all the electrical signal lines available on the memory bus, and could issue data access commands to different groups of nonvolatile memory devices over different groups of electrical signal lines. The memory bus may be available and configured for either use with a memory controller and volatile memory devices, or a storage controller and nonvolatile memory devices.

    摘要翻译： 通过存储器总线访问非易失性存储器或存储器件。 存储器总线具有通常用于易失性存储器件的电接口。 耦合到总线的控制器向非易失性存储器件发送同步数据访问命令，并且基于来自非易失性存储器件的回复的期望定时从设备总线读取响应。 控制器基于何时发送命令和非易失性存储器件的特性来确定预期时序。 控制器可能不需要存储器总线上可用的所有电信号线，并且可以通过不同的电信号线组向不同组的非易失性存储器件发出数据访问命令。 存储器总线可以可用并且被配置用于与存储器控制器和易失性存储器设备或存储控制器和非易失性存储器设备一起使用。

    Methods and apparatus to train interdependent autonomous machines
    9.
    发明授权
    Methods and apparatus to train interdependent autonomous machines 有权

    公开(公告)号：US11292133B2

    公开(公告)日：2022-04-05

    申请号：US16145796

    申请日：2018-09-28

    申请人： Intel Corporation

    发明人： Rita H. Wouhaybi ,  Shekoufeh Qawami ,  Hassnaa Moustafa ,  Chaitanya Sreerama ,  Nadine L. Dabby

    IPC分类号： G05B19/04 ,  B25J9/16 ,  G06N3/08 ,  G06N5/04 ,  G06N20/00 ,  G06N3/04 ,  G06N3/00

    摘要： Methods and apparatus to train interdependent autonomous machines are disclosed. An example method includes performing an action of a first sub-task of a collaborative task with a first collaborative robot in a robotic cell while a second collaborative robot operates in the robotic cell according to a first recorded action of the second collaborative robot, the first recorded action of the second collaborative robot recorded while a second robot controller associated with the second collaborative robot is trained to control the second collaborative robot to perform a second sub-task of the collaborative task, and training a first robot controller associated with the first collaborative robot based at least on a sensing of an interaction of the first collaborative robot with the second collaborative robot while the action of the first sub-task is performed by the first collaborative robot and the second collaborative robot operates according to the first recorded action.