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    ELECTRONIC DEVICE PACKAGE
    2.
    发明申请
    ELECTRONIC DEVICE PACKAGE 审中-公开

    公开(公告)号：US20190228988A1

    公开(公告)日：2019-07-25

    申请号：US16373615

    申请日：2019-04-02

    申请人： Intel Corporation

    发明人： Jimin Yao ,  Eric Li ,  Shawna Liff

    IPC分类号： H01L21/56 ,  H01L23/31

    摘要： Electronic device package technology is disclosed. In one example, an electronic device package can include a substrate, an electronic component disposed on the substrate and electrically coupled to the substrate, and an underfill material disposed at least partially between the electronic component and the substrate. A lateral portion of the underfill material can comprises a lateral surface extending away from the substrate and a meniscus surface extending between the lateral surface and the electronic component.

    Stacked die package with through-mold thermally conductive structures between a bottom die and a thermally conductive material
    4.
    发明授权
    Stacked die package with through-mold thermally conductive structures between a bottom die and a thermally conductive material 有权

    公开(公告)号：US10541190B2

    公开(公告)日：2020-01-21

    申请号：US15769705

    申请日：2015-11-30

    申请人： Intel Corporation

    发明人： Chandra Jha ,  Eric Li

    IPC分类号： H01L23/433 ,  H01L23/24 ,  H01L23/31 ,  H01L23/367 ,  H01L23/373

    摘要： An apparatus is described that includes a first semiconductor die. A second semiconductor die is stacked on the first semiconductor die. The first semiconductor die has a larger surface area than the second semiconductor die such that there exists a peripheral region of the first semiconductor die that is not covered by the second semiconductor die. The apparatus includes thermally conductive material above the second semiconductor die. The apparatus includes a compound mold between the thermally conductive material and both the second semiconductor die and the peripheral region of the first semiconductor die. The apparatus includes a thermally conductive structure extending through the compound mold that thermally couples the peripheral region to the thermally conductive material.

    Electronic device packages with conformal EMI shielding and related methods
    6.
    发明授权
    Electronic device packages with conformal EMI shielding and related methods 有权

    公开(公告)号：US10325866B2

    公开(公告)日：2019-06-18

    申请号：US15847193

    申请日：2017-12-19

    申请人： Intel Corporation

    发明人： Eric Li ,  Joshua Heppner ,  Rajendra Dias ,  Mitul Modi

    IPC分类号： H01L23/60 ,  H01L21/78 ,  H01L23/31 ,  H01L21/56 ,  H01L23/552 ,  H01L23/00

    摘要： Electronic device package technology is disclosed. In one example, an electronic device package can include a bottom surface and a side surface extending from the bottom surface. The side surface can be oriented at a non-perpendicular angle relative to the bottom surface. In another example, an electronic device package can include a top planar surface having a first area, a bottom planar surface having a second area, and a side surface extending between the top surface and the bottom surface. The second area can be larger than the first area. In yet another example, an electronic device package can include a substrate defining a plane, an electronic component disposed on the substrate, and a layer of material disposed about a lateral side of the electronic component. The layer of material can be oriented at an angle of less than 90 degrees relative to the plane.

    FINE FEATURE FORMATION TECHNIQUES FOR PRINTED CIRCUIT BOARDS
    9.
    发明申请
    FINE FEATURE FORMATION TECHNIQUES FOR PRINTED CIRCUIT BOARDS 有权

    公开(公告)号：US20210352807A1

    公开(公告)日：2021-11-11

    申请号：US17383084

    申请日：2021-07-22

    申请人： INTEL CORPORATION

    发明人： Eric Li ,  Kemal Aygun ,  Kai Xiao ,  Gong Ouyang ,  Zhichao Zhang

    IPC分类号： H05K3/00 ,  H05K3/02 ,  H05K1/02

    摘要： Fine feature formation techniques for printed circuit boards are described. In one embodiment, for example, a method may comprise fabricating a conductive structure on a low density interconnect (LDI) printed circuit board (PCB) according to an LDI fabrication process and forming one or more fine conductive features on the LDI PCB by performing a fine feature formation (FFF) process, the FFF process to comprise removing conductive material of the conductive structure along an excision path to form a fine gap region within the conductive structure. Other embodiments are described and claimed.

    Fine feature formation techniques for printed circuit boards
    10.
    发明授权
    Fine feature formation techniques for printed circuit boards 有权

    公开(公告)号：US11089689B2

    公开(公告)日：2021-08-10

    申请号：US16081487

    申请日：2016-04-02

    申请人： INTEL CORPORATION

    发明人： Eric Li ,  Kemal Aygun ,  Kai Xiao ,  Gong Ouyang ,  Zhichao Zhang

    IPC分类号： H05K3/00 ,  H05K3/02 ,  H05K1/02 ,  H05K3/46

    摘要： Fine feature formation techniques for printed circuit boards are described. In one embodiment, for example, a method may comprise fabricating a conductive structure 306 on a low density interconnect (LDI) printed circuit board (PCB) 150 according to an LDI fabrication process and forming one or more fine conductive features on the LDI PCB by performing a fine feature formation (FFF) process, the FFF process to comprise removing conductive material of the conductive structure along an excision path to form a fine gap region 308 within the conductive structure. Other embodiments are described and claimed.