公开(公告)号：US11837641B2

公开(公告)日：2023-12-05

申请号：US16719281

申请日：2019-12-18

申请人： Intel Corporation

发明人： Biswajeet Guha ,  William Hsu ,  Chung-Hsun Lin ,  Kinyip Phoa ,  Oleg Golonzka ,  Tahir Ghani ,  Kalyan Kolluru ,  Nathan Jack ,  Nicholas Thomson ,  Ayan Kar ,  Benjamin Orr

IPC分类号： H01L29/41 ,  H01L29/417 ,  H01L25/18 ,  H01L27/088 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/41791 ,  H01L25/18 ,  H01L27/0886 ,  H01L29/0673 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/6653 ,  H01L29/6681 ,  H01L29/7853 ,  H01L2029/7858

摘要： Gate-all-around integrated circuit structures having adjacent deep via substrate contact for sub-fin electrical contact are described. For example, an integrated circuit structure includes a conductive via on a semiconductor substrate. A vertical arrangement of horizontal nanowires is above a fin protruding from the semiconductor substrate. A channel region of the vertical arrangement of horizontal nanowires is electrically isolated from the fin. The fin is electrically coupled to the conductive via. A gate stack is over the vertical arrangement of horizontal nanowires.

公开(公告)号：US11908856B2

公开(公告)日：2024-02-20

申请号：US16719257

申请日：2019-12-18

申请人： Intel Corporation

发明人： Biswajeet Guha ,  William Hsu ,  Chung-Hsun Lin ,  Kinyip Phoa ,  Oleg Golonzka ,  Tahir Ghani ,  Kalyan Kolluru ,  Nathan Jack ,  Nicholas Thomson ,  Ayan Kar ,  Benjamin Orr

IPC分类号： H01L27/088 ,  H01L29/78 ,  H01L29/06

CPC分类号： H01L27/0886 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/785

摘要： Gate-all-around structures having devices with source/drain-to-substrate electrical contact are described. An integrated circuit structure includes a first vertical arrangement of horizontal nanowires above a first fin. A first gate stack is over the first vertical arrangement of horizontal nanowires. A first pair of epitaxial source or drain structures is at first and second ends of the first vertical arrangement of horizontal nanowires. One or both of the first pair of epitaxial source or drain structures is directly electrically coupled to the first fin. A second vertical arrangement of horizontal nanowires is above a second fin. A second gate stack is over the second vertical arrangement of horizontal nanowires. A second pair of epitaxial source or drain structures is at first and second ends of the second vertical arrangement of horizontal nanowires. Both of the second pair of epitaxial source or drain structures is electrically isolated from the second fin.

公开(公告)号：US20230307449A1

公开(公告)日：2023-09-28

申请号：US17656490

申请日：2022-03-25

申请人： Intel Corporation

发明人： Tao Chu ,  Minwoo Jang ,  Aurelia Chi Wang ,  Conor Puls ,  Brian Greene ,  Tofizur Rahman ,  Lin Hu ,  Jaladhi Mehta ,  Chung-Hsun Lin ,  Walid Hafez

IPC分类号： H01L27/088 ,  H01L29/06 ,  H01L29/423

CPC分类号： H01L27/088 ,  H01L29/0665 ,  H01L29/42392

摘要： An integrated circuit includes a first source region, a first drain region, a first fin having (i) a first upper region laterally between the first source region and the first drain region and (ii) a first lower region below the first upper region, and a first gate structure on at least top and side surfaces of the first upper region. The integrated circuit further includes a second source region, a second drain region, a second fin having (i) a second upper region laterally between the second source region and the second drain region and (ii) a second lower region below the second upper region, and a second gate structure on at least top and side surfaces of the second upper region. In an example, a first vertical height of the first lower region is different from a second vertical height of the second lower region by at least 2 nanometers (nm).

公开(公告)号：US20240088132A1

公开(公告)日：2024-03-14

申请号：US17943819

申请日：2022-09-13

申请人： Intel Corporation

发明人： Nicholas A. Thomson ,  Kalyan C. Kolluru ,  Ayan Kar ,  Chu-Hsin Liang ,  Benjamin Orr ,  Biswajeet Guha ,  Brian Greene ,  Chung-Hsun Lin ,  Sabih U. Omar ,  Sameer Jayanta Joglekar

IPC分类号： H01L27/02 ,  H01L29/06 ,  H01L29/861

CPC分类号： H01L27/0255 ,  H01L29/0673 ,  H01L29/8611

摘要： An integrated circuit structure includes a sub-fin having (i) a first portion including a p-type dopant and (ii) a second portion including an n-type dopant. A first body of semiconductor material is above the first portion of the sub-fin, and a second body of semiconductor material is above the second portion of the sub-fin. In an example, the first portion of the sub-fin and the second portion of the sub-fin are in contact with each other, to form a PN junction of a diode. For example, the first portion of the sub-fin is part of an anode of the diode, and wherein the second portion of the sub-fin is part of a cathode of the diode.

公开(公告)号：US11824116B2

公开(公告)日：2023-11-21

申请号：US16719222

申请日：2019-12-18

申请人： Intel Corporation

发明人： Biswajeet Guha ,  William Hsu ,  Chung-Hsun Lin ,  Kinyip Phoa ,  Oleg Golonzka ,  Ayan Kar ,  Nicholas Thomson ,  Benjamin Orr ,  Nathan Jack ,  Kalyan Kolluru ,  Tahir Ghani

IPC分类号： H01L29/78 ,  H01L29/423 ,  H01L29/06 ,  H01L29/417

CPC分类号： H01L29/7831 ,  H01L29/0669 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/785

摘要： Gate-all-around integrated circuit structures having devices with channel-to-substrate electrical contact are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires above a first fin. A channel region of the first vertical arrangement of horizontal nanowires is electrically coupled to the first fin by a semiconductor material layer directly between the first vertical arrangement of horizontal nanowires and the first fin. A first gate stack is over the first vertical arrangement of horizontal nanowires. A second vertical arrangement of horizontal nanowires is above a second fin. A channel region of the second vertical arrangement of horizontal nanowires is electrically isolated from the second fin. A second gate stack is over the second vertical arrangement of horizontal nanowires.

公开(公告)号：US11799009B2

公开(公告)日：2023-10-24

申请号：US16716907

申请日：2019-12-17

申请人： Intel Corporation

发明人： Biswajeet Guha ,  William Hsu ,  Chung-Hsun Lin ,  Kinyip Phoa ,  Oleg Golonzka ,  Tahir Ghani

IPC分类号： H01L29/423 ,  H01L27/088 ,  H01L29/786 ,  H01L29/417

CPC分类号： H01L29/42392 ,  H01L27/0886 ,  H01L29/41733 ,  H01L29/41791 ,  H01L29/78696

摘要： Gate-all-around integrated circuit structures having adjacent structures for sub-fin electrical contact are described. For example, an integrated circuit structure includes a semiconductor island on a semiconductor substrate. A vertical arrangement of horizontal nanowires is above a fin protruding from the semiconductor substrate. A channel region of the vertical arrangement of horizontal nanowires is electrically isolated from the fin. The fin is electrically coupled to the semiconductor island. A gate stack is over the vertical arrangement of horizontal nanowires.

公开(公告)号：US20220199472A1

公开(公告)日：2022-06-23

申请号：US17132995

申请日：2020-12-23

申请人： Intel Corporation

发明人： Robin Chao ,  Bishwajeet Guha ,  Brian Greene ,  Chung-Hsun Lin ,  Curtis Tsai ,  Orb Acton

IPC分类号： H01L21/8234 ,  H01L27/088 ,  H01L27/12 ,  H01L21/84

摘要： Integrated circuitry comprising high voltage (HV) and low voltage (LV) ribbon or wire (RoW) transistor stack structures. In some examples, a gate electrode of the HV and LV transistor stack structures may include the same work function metal. A metal oxide may be deposited around one or more channels of the HV transistor stack, thereby altering the dipole properties of the gate insulator stack from those of the LV transistor stack structure.

公开(公告)号：US20210408289A1

公开(公告)日：2021-12-30

申请号：US16914145

申请日：2020-06-26

申请人： Intel Corporation

发明人： Biswajeet Guha ,  Brian Greene ,  Robin Chao ,  Adam Faust ,  Chung-Hsun Lin ,  Curtis Tsai ,  Kevin Fischer

IPC分类号： H01L29/78 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66

摘要： A transistor structure includes a first channel layer over a second channel layer, where the first and the second channel layers include monocrystalline silicon. An epitaxial source material is coupled to a first end of the first and second channel layers. An epitaxial drain material is coupled to a second end of the first and second channel layers, a gate electrode is between the epitaxial source material and the epitaxial drain material, and around the first channel layer and around the second channel layer. The transistor structure further includes a first gate dielectric layer between the gate electrode and each of the first channel layer and the second channel layer, where the first gate dielectric layer has a first dielectric constant. A second gate dielectric layer is between the first gate dielectric layer and the gate electrode, where the second gate dielectric layer has a second dielectric constant.

公开(公告)号：US11869987B2

公开(公告)日：2024-01-09

申请号：US17860056

申请日：2022-07-07

申请人： Intel Corporation

发明人： Ayan Kar ,  Saurabh Morarka ,  Carlos Nieva-Lozano ,  Kalyan Kolluru ,  Biswajeet Guha ,  Chung-Hsun Lin ,  Brian Greene ,  Tahir Ghani

IPC分类号： H01L29/06 ,  H01L29/93 ,  H01L29/66 ,  H01L21/02

CPC分类号： H01L29/93 ,  H01L21/02532 ,  H01L21/02603 ,  H01L29/0673 ,  H01L29/66174

摘要： Gate-all-around integrated circuit structures including varactors are described. For example, an integrated circuit structure includes a varactor structure on a semiconductor substrate. The varactor structure includes a plurality of discrete vertical arrangements of horizontal nanowires. A plurality of gate stacks is over and surrounding corresponding ones of the plurality of discrete vertical arrangements of horizontal nanowires. The integrated circuit structure also includes a tap structure adjacent to the varactor structure on the semiconductor substrate. The tap structure includes a plurality of merged vertical arrangements of horizontal nanowires. A plurality of semiconductor structures is over and surrounding corresponding ones of the plurality of merged vertical arrangements of horizontal nanowires.

公开(公告)号：US20230071699A1

公开(公告)日：2023-03-09

申请号：US17470993

申请日：2021-09-09

申请人： Intel Corporation

发明人： Andrew Smith ,  Brian Greene ,  Seonghyun Paik ,  Omair Saadat ,  Chung-Hsun Lin ,  Tahir Ghani

IPC分类号： H01L29/423 ,  H01L29/786 ,  H01L27/092 ,  H01L29/06 ,  H01L21/8238

摘要： A transistor structure includes a channel region including first sidewall. A gate electrode includes a first layer having a first portion adjacent to the first sidewall and a second portion adjacent to a gate electrode boundary sidewall. The gate electrode includes a second layer between the first and second portions of the first layer. The first layer has a first composition associated with a first work function material, and has a first lateral thickness from the first sidewall. The second layer has a second composition associated with a second work function material. Depending one a second lateral thickness of the second layer, the second layer may modulate a threshold voltage (VT) of the transistor structure by more or less. In some embodiments, a ratio of the second lateral thickness to the first lateral thickness is less than three.