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公开(公告)号：US11916568B2
公开(公告)日：2024-02-27
申请号：US17652960
申请日：2022-03-01
发明人： Marcel A. Kossel , Pier Andrea Francese , Abdullah Serdar Yonar , Mridula Prathapan , Thomas Morf
摘要： A hierarchical time step generator circuit is configured to be used for a time-based analog-to-digital converter. The hierarchical time step generator is configured to generate multiphase clock signals in response to receiving a reference clock signal. The time-based analog-to-digital converter is configured to be controlled to digitize the input signal by the multiphase clock signals. The hierarchical time step generator includes a first level time step generator configured to generate the a set of first level multiphase signals in response to receiving the reference clock signal a phase interpolator circuit configured as second level to generate second level clock signals between each of the first level clock signals and a third level configured to generate the third set of multiphase clock signals using a set of time staggered multi-phase phase locked loops synchronized to each of the second level clock signals.
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公开(公告)号：US11811418B2
公开(公告)日：2023-11-07
申请号：US17652957
申请日：2022-03-01
发明人： Marcel A. Kossel , Pier Andrea Francese , Abdullah Serdar Yonar , Mridula Prathapan , Thomas Morf
摘要： Disclosed herein is an analog-to-digital converter circuit configured for digitizing an analog input signal. The analog-to-digital converter comprises an analog input configured for receiving the analog input signal. The analog-to-digital converter circuit further comprises at least one sub-ADC connected to the analog input signal, wherein the at least one sub-ADC is configured to output at least one encoded output vector in response to receiving the analog input signal. The analog-to-digital converter circuit further comprises a lookup circuit comprising a nested lookup table. The lookup circuit is configured to select an output value from the nested lookup table using the at least one encoded output vector, wherein the lookup circuit is configured to provide the output value as the digitization of the analog input signal.
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公开(公告)号：US20230139805A1
公开(公告)日：2023-05-04
申请号：US17453499
申请日：2021-11-04
发明人： Thomas Morf , Cezar Bogdan Zota , Peter Mueller , Pier Andrea Francese , Marcel A. Kossel , Matthias Braendli , Mridula Prathapan
摘要： The invention relates to a control unit for controlling a data transfer between a classical processor and a quantum processor with a plurality of qubits. The control unit comprises a plurality of control and read-out circuits configured for controlling and reading out the plurality of qubits. Each of the control and read-out circuits is assigned to one or more of the qubits. A controlling of the quantum processor by the control unit comprises selectively powering on a subset of the control and read-out circuits during an instruction cycle, while ensuring that the remaining control and read-out circuits are powered off during the instruction cycle. The powered-on subset of control and read-out circuits is used to control a subset of the qubits and to read out data from the subset of qubits.
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公开(公告)号：US11499998B2
公开(公告)日：2022-11-15
申请号：US16524681
申请日：2019-07-29
摘要： Embodiments of the invention are directed to a current sensor that includes a current controlled oscillator circuit configured to receive an input current and to provide an output signal having an output frequency which is dependent on the input current. The current sensor further includes a feedforward circuit configured to adapt a reference voltage of the current controlled oscillator in dependence on an instantaneous current value of the input current.
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公开(公告)号：US20210033648A1
公开(公告)日：2021-02-04
申请号：US16524681
申请日：2019-07-29
摘要： Embodiments of the invention are directed to a current sensor that includes a current controlled oscillator circuit configured to receive an input current and to provide an output signal having an output frequency which is dependent on the input current. The current sensor further includes a feedforward circuit configured to adapt a reference voltage of the current controlled oscillator in dependence on an instantaneous current value of the input current.
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6.发明授权Continuous time linear equalizer with a programmable negative feedback amplification loop 有权具有可编程负反馈放大回路的连续时间线性均衡器公开(公告)号：US09473330B1
公开(公告)日：2016-10-18
申请号：US14732273
申请日：2015-06-05
发明人： Pier Andrea Francese
CPC分类号： H04L25/03057 , H04B1/123 , H04L25/03267 , H04L25/03885
摘要： A continuous time linear equalizer and method of operation. The equalizer includes circuitry configured to provide a high-pass transfer function having a peaking frequency to equalize an input signal into an output signal. The circuitry includes an input gain stage configured to receive an input signal and to provide a gain; and an active peaking stage configured to set the gain at a peaking frequency. A bandwidth extension unit is configured to shift the peaking frequency of the continuous time linear equalizer to a higher frequency.
摘要翻译： 连续时间线性均衡器和操作方法。 均衡器包括被配置为提供具有峰值频率以将输入信号均衡为输出信号的高通传递函数的电路。 该电路包括输入增益级，配置为接收输入信号并提供增益; 以及激活峰化阶段，用于将增益设置为峰值频率。 带宽扩展单元被配置为将连续时间线性均衡器的峰值频率移位到更高的频率。
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公开(公告)号：US20230283290A1
公开(公告)日：2023-09-07
申请号：US17652960
申请日：2022-03-01
发明人： Marcel A. Kossel , Pier Andrea Francese , Abdullah Serdar Yonar , Mridula Prathapan , Thomas Morf
摘要： Disclosed herein is a hierarchical time step generator circuit configured to be used for a time-based analog-to-digital converter. The hierarchical time step generator is configured to generate multiphase clock signals in response to receiving a reference clock signal. The time-based analog-to-digital converter is configured to be controlled to digitize the input signal by the multiphase clock signals. The hierarchical time step generator comprises: a first level time step generator configured to generate the a set of first level multiphase signals in response to receiving the reference clock signal; a phase interpolator circuit configured as second level to generate second level clock signals between each of the first level clock signals; and a third level configured to generate the third set of multiphase clock signals using a set of time staggered multi-phase phase locked loops synchronized to each of the second level clock signals.
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公开(公告)号：US11531898B2
公开(公告)日：2022-12-20
申请号：US16413738
申请日：2019-05-16
发明人： Manuel Le Gallo-Bourdeau , Riduan Khaddam-Aljameh , Lukas Kull , Pier Andrea Francese , Thomas H. Toifl , Abu Sebastian , Evangelos Stavros Eleftheriou
摘要： Methods and apparatus are provided for training an artificial neural network having a succession of neuron layers with interposed synaptic layers each having a respective set of N-bit fixed-point weights {w} for weighting signals propagated between its adjacent neuron layers, via an iterative cycle of signal propagation and weight-update calculation operations. Such a method includes, for each synaptic layer, storing a plurality p of the least-significant bits of each N-bit weight w in digital memory, and storing the next n-bit portion of each weight w in an analog multiply-accumulate unit comprising an array of digital memory elements. Each digital memory element comprises n binary memory cells for storing respective bits of the n-bit portion of a weight, where n≥1 and (p+n+m)=N where m≥0 corresponds to a defined number of most-significant zero bits in weights of the synaptic layer.
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公开(公告)号：US20220350514A1
公开(公告)日：2022-11-03
申请号：US17242392
申请日：2021-04-28
摘要： A memory controller circuit for mapping data of a convolutional neural network to a physical memory is disclosed. The memory controller circuit comprises a receiving unit to receive a selection parameter value, and a mapping unit to map pixel values of one layer of the convolutional neural network to memory words of the physical memory according to one of a plurality of mapping schemas, wherein the mapping is dependent on the value of the received selection parameter value.
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公开(公告)号：US20220302698A1
公开(公告)日：2022-09-22
申请号：US17745958
申请日：2022-05-17
发明人： Thomas Morf , Pier Andrea Francese
摘要： An electrostatic protection device for protecting an input port of an electronic circuit. The electrostatic protection device includes a first stacked coil, a second stacked coil, and an input terminal, wherein the second stacked coil is inductively coupled to the first stacked coil. The first stacked coil comprises a first coil input connected to the input terminal, and a first coil output port connected to a lower frequency ESD protection circuit, and wherein the lower frequency ESD protection circuit comprises a lower frequency output. The second stacked coil comprises an output port connected to a higher frequency ESD protection circuit, and wherein the higher frequency ESD protection circuit comprises a higher frequency output.
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