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公开(公告)号：US20190173586A1
公开(公告)日：2019-06-06
申请号：US16272497
申请日：2019-02-11
发明人： Alessandro Cevrero , Pier Andrea Francese , Marcel A. Kossel , Christian I. Menolfi , Ilter Özkaya , Thomas H. Toifl
IPC分类号： H04B10/50 , H04B10/524 , H03F1/06
摘要： A system and method for a high-speed transmitter comprising a precoder configured to receive a sequence of input symbols and to generate for each received symbol a respective recoded symbol is disclosed. The transmitter includes a recoding unit configured for recoding each current received PAM-M based on the recoded symbol immediately preceding the current recoded symbol at the recoding unit, a shift unit configured for determining a shift value for each current received symbol from the recoding unit based on the symbol received from the recoding unit and immediately preceding the current symbol at the shift unit; and Feed-Forward Equalizer unit for applying the shift values to the respective symbols received from the recoding unit to generate a corresponding sequence of output symbols to be transmitted in an output stream.
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公开(公告)号：US09300498B2
公开(公告)日：2016-03-29
申请号：US14745520
申请日：2015-06-22
发明人： Thomas H. Toifl , Hazar Yüksel
CPC分类号： H04L25/03057 , H04L2025/03503
摘要： A decision-feedback equalizer for use in a receiving unit of an incoming data stream and for providing a stream of bit data outputs includes a number of comparators configured to perform a comparison related to a number of threshold values and related to a digitalized data sample and to obtain a comparison result; at least one correction block configured to receive the comparison result of a respective one of the comparators and to generate a plurality of intermediate results; and a multiplexer configured to select from the set of intermediate results depending on the output data history to provide the stream of bit data outputs.
摘要翻译： 用于输入数据流的接收单元和用于提供位数据输出流的判决反馈均衡器包括多个比较器，其被配置为执行与多个阈值相关并且与数字化数据样本相关的比较，以及 获得比较结果; 至少一个校正块被配置为接收所述比较器中的相应一个比较器的比较结果并产生多个中间结果; 以及多路复用器，其被配置为根据输出数据历史从该组中间结果中选择以提供比特数据输出流。
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公开(公告)号：US20150312064A1
公开(公告)日：2015-10-29
申请号：US14745533
申请日：2015-06-22
IPC分类号： H04L25/03
CPC分类号： H04L25/03057 , H04B1/123 , H04L25/03063 , H04L25/03885
摘要： A continuous-time linear equalizer for use in a receiving unit of a high-speed data transmission system for receiving an input signal includes a signal line configured to provide an equalized output voltage, and an active peaking control unit, including a predetermined first number of active peaking transistors each coupled between the signal line and a power supply rail; a peaking resistor that couples gate terminals of each of the active peaking transistors to the signal line; and a first number of first setting switches each associated with each of the first number of active peaking transistors to activate a predetermined number of the first number of transistors according to first setting signals.
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公开(公告)号：US20150180648A1
公开(公告)日：2015-06-25
申请号：US14561554
申请日：2014-12-05
发明人： Pier A. Francese , Lukas Kull , Thomas H. Toifl
IPC分类号： H04L7/02
CPC分类号： H04L7/02 , H04L7/0334
摘要： The invention relates to a phase rotation method for a clock recovery, comprising the steps of: providing a timing estimation value that indicates for each input data symbol at least whether an input data sample has been sampled early or late by a sampling clock signal; generating a phase offset value indicating a phase rotation of the sampling clock signal based on the timing estimation value; modifying the timing function value based on a change of the phase offset value, resulting in the timing estimation value.
摘要翻译： 本发明涉及一种用于时钟恢复的相位旋转方法，包括以下步骤：提供定时估计值，该定时估计值至少指示输入数据样本是否已经被采样时钟信号早或晚地采样， 基于所述定时估计值产生指示所述采样时钟信号的相位旋转的相位偏移值; 基于相位偏移值的变化来修正定时功能值，得到定时估计值。
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公开(公告)号：US10243591B2
公开(公告)日：2019-03-26
申请号：US15251638
申请日：2016-08-30
摘要： Sequence detectors and detection methods are provided for detecting symbol values corresponding to a sequence of input samples obtained from an ISI channel. The sequence detector comprises a branch metric unit (BMU) and a path metric unit (PMU). The BMU, which comprises an initial set of pipeline stages, is adapted to calculate, for each input sample, branch metrics for respective possible transitions between states of a trellis. To calculate these branch metrics, the BMU selects hypothesized input values, each dependent on a possible symbol value for the input sample and L>0 previous symbol values corresponding to possible transitions between states of the trellis. The BMU then calculates differences between the input sample and each hypothesized input value. The BMU compares these differences and selects, as the branch metric for each possible transition, an optimum difference in dependence on a predetermined state in a survivor path through the trellis.
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公开(公告)号：US10205525B1
公开(公告)日：2019-02-12
申请号：US15827960
申请日：2017-11-30
发明人： Alessandro Cevrero , Pier Andrea Francese , Marcel A. Kossel , Christian I. Menolfi , Ilter Özkaya , Thomas H. Toifl
IPC分类号： H04B10/04 , H04B10/50 , H04B10/524 , H03F1/06
摘要： A system and method for a high-speed transmitter comprising a precoder configured to receive a sequence of input symbols and to generate for each received symbol a respective recoded symbol is disclosed. The transmitter includes a recoding unit configured for recoding each current received PAM-M based on the recoded symbol immediately preceding the current recoded symbol at the recoding unit, a shift unit configured for determining a shift value for each current received symbol from the recoding unit based on the symbol received from the recoding unit and immediately preceding the current symbol at the shift unit; and Feed-Forward Equalizer unit for applying the shift values to the respective symbols received from the recoding unit to generate a corresponding sequence of output symbols to be transmitted in an output stream.
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公开(公告)号：US10142090B1
公开(公告)日：2018-11-27
申请号：US15702811
申请日：2017-09-13
摘要： Octagonal phase rotator apparatus is provided for producing an output signal that is phase dependent on a digital control code. The apparatus includes an I-mixer, a Q-mixer, and first and second IQ-mixers. The I-mixer is responsive to I-control bits of the digital control code. The Q-mixer is responsive to Q-control bits of the digital control code. The first and second IQ-mixers are respectively responsive to one or more IQ1-control bits and one or more IQ2-control bits of the digital control code. The I-mixer comprises an I-DAC for steering current between a positive phase IP and a negative phase IN of an in-phase (I) signal wherein the one or more I-control bits control switching of a first current unit between IP and IN, and a set of amplifiers for weighting the phases IP and IN, in dependence on current steered to each phase by the I-DAC, to produce a weighted I-signal.
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公开(公告)号：US20180062790A1
公开(公告)日：2018-03-01
申请号：US15251673
申请日：2016-08-30
IPC分类号： H04L1/00
CPC分类号： H04L1/0054 , H03M13/3977 , H03M13/4115 , H03M13/4169 , H04L1/0052 , H04L1/006 , H04L25/03
摘要： A sequence detector is provided for detecting symbol values corresponding to a sequence of input samples obtained from a transmission channel. The sequence detector comprises a branch metric unit (BMU), a path metric unit (PMU) and a survivor memory unit. The branch metric unit calculates branch metrics for respective possible transitions between states of a trellis. The path metric unit accumulates branch metrics provided by the branch metric unit in order to establish path metrics. The survivor memory unit selects a survivor path based on the path metrics and outputs a survivor sequence of the detected symbols corresponding to the survivor path. The sequence detector is configured such that the synchronization length is different than the survivor path memory length.
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9.发明授权Third order harmonic distortion correction circuit using a reference analog digital converter 有权三阶谐波失真校正电路采用参考模拟数字转换器公开(公告)号：US09461661B1
公开(公告)日：2016-10-04
申请号：US15008733
申请日：2016-01-28
CPC分类号： H03M1/10 , H03M1/0678 , H03M1/1042 , H03M1/1245 , H03M1/38
摘要： A linear reference analog to digital converter (ADC) network may include a first ADC operatively connected to a first sample and hold circuit. The linear reference ADC network may be configured to receive an input signal from the first sample and hold circuit and sample the input signal with a harmonic distortion. The linear reference ADC network may further include a reference ADC operatively connected to a second sample and hold circuit and configured to receive the input signal and sample the input signal with a second harmonic distortion. The linear reference ADC network may further include a combining module operatively connected to the first ADC and the reference ADC, the combining module configured to equalize a linearity of an output of the first ADC to a linearity of an output of the reference ADC, and output a combined output signal, and a circuit configured to output a calibrated output signal having calibrated harmonic distortion content.
摘要翻译： 线性参考模数转换器（ADC）网络可以包括可操作地连接到第一采样和保持电路的第一ADC。 线性参考ADC网络可以被配置为从第一采样和保持电路接收输入信号并且对谐波失真的输入信号进行采样。 线性参考ADC网络还可以包括可操作地连接到第二采样和保持电路的参考ADC，并且被配置为接收输入信号并用二次谐波失真对输入信号进行采样。 线性参考ADC网络还可以包括可操作地连接到第一ADC和参考ADC的组合模块，所述组合模块被配置为将第一ADC的输出的线性度与参考ADC的输出的线性度相等，并且输出 组合输出信号，以及被配置为输出具有校准的谐波失真内容的校准输出信号的电路。
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公开(公告)号：US09288085B2
公开(公告)日：2016-03-15
申请号：US14669225
申请日：2015-03-26
CPC分类号： H04L25/03057 , H04B1/123 , H04L25/03063 , H04L25/03885
摘要： A continuous-time linear equalizer for use in a receiving unit of a high-speed data transmission system for receiving an input signal includes a signal line configured to provide an equalized output voltage, and an active peaking control unit, including a predetermined first number of active peaking transistors each coupled between the signal line and a power supply rail; a peaking resistor that couples gate terminals of each of the active peaking transistors to the signal line; and a first number of first setting switches each associated with each of the first number of active peaking transistors to activate a predetermined number of the first number of transistors according to first setting signals.
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