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公开(公告)号：US20150312064A1
公开(公告)日：2015-10-29
申请号：US14745533
申请日：2015-06-22
IPC分类号： H04L25/03
CPC分类号： H04L25/03057 , H04B1/123 , H04L25/03063 , H04L25/03885
摘要： A continuous-time linear equalizer for use in a receiving unit of a high-speed data transmission system for receiving an input signal includes a signal line configured to provide an equalized output voltage, and an active peaking control unit, including a predetermined first number of active peaking transistors each coupled between the signal line and a power supply rail; a peaking resistor that couples gate terminals of each of the active peaking transistors to the signal line; and a first number of first setting switches each associated with each of the first number of active peaking transistors to activate a predetermined number of the first number of transistors according to first setting signals.
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2.发明授权公开(公告)号：US09460383B2
公开(公告)日：2016-10-04
申请号：US14475409
申请日：2014-09-02
发明人： Bernard V. Brezzo , Leland Chang , Steven K. Esser , Daniel J. Friedman , Yong Liu , Dharmendra S. Modha , Robert K. Montoye , Bipin Rajendran , Jae-sun Seo , Jose A. Tierno
IPC分类号： G06N3/063
摘要： A reconfigurable neural network circuit is provided. The reconfigurable neural network circuit comprises an electronic synapse array including multiple synapses interconnecting a plurality of digital electronic neurons. Each neuron comprises an integrator that integrates input spikes and generates a signal when the integrated inputs exceed a threshold. The circuit further comprises a control module for reconfiguring the synapse array. The control module comprises a global final state machine that controls timing for operation of the circuit, and a priority encoder that allows spiking neurons to sequentially access the synapse array.
摘要翻译： 提供可重构神经网络电路。 可重构神经网络电路包括电子突触阵列，其包括互连多个数字电子神经元的多个突触。 每个神经元包括积分器，其对输入尖峰进行积分，并且当集成输入超过阈值时产生信号。 电路还包括用于重新配置突触阵列的控制模块。 控制模块包括控制电路操作的定时的全局最终状态机，以及允许加标神经元依次访问突触阵列的优先编码器。
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公开(公告)号：US09288085B2
公开(公告)日：2016-03-15
申请号：US14669225
申请日：2015-03-26
CPC分类号： H04L25/03057 , H04B1/123 , H04L25/03063 , H04L25/03885
摘要： A continuous-time linear equalizer for use in a receiving unit of a high-speed data transmission system for receiving an input signal includes a signal line configured to provide an equalized output voltage, and an active peaking control unit, including a predetermined first number of active peaking transistors each coupled between the signal line and a power supply rail; a peaking resistor that couples gate terminals of each of the active peaking transistors to the signal line; and a first number of first setting switches each associated with each of the first number of active peaking transistors to activate a predetermined number of the first number of transistors according to first setting signals.
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4.发明授权Distributed phase detection for clock synchronization in multi-layer 3D stacks 有权分层相位检测用于多层3D堆叠中的时钟同步公开(公告)号：US09231603B2
公开(公告)日：2016-01-05
申请号：US14230859
申请日：2014-03-31
发明人： Yong Liu , Liang-Teck Pang , Phillip J. Restle
CPC分类号： H03L7/087 , G06F1/12 , H03L7/0812
摘要： There is provided a clock distribution network for synchronizing global clock signals within a 3D chip stack having two or more strata. The clock distribution circuit includes, on each of the two or more strata, phase detectors, a logic circuit, and a phase de-skewing element. Each phase detector has a respective output for providing phase information relating to a phase difference between two of the global clocks signals on respective different ones of the two or more strata. The logic circuit is connected to the respective outputs of the phase detectors for determining a phase adjustment plan for a given one of the two or more strata upon which the logic circuit is located responsive to the phase information. The phase de-skewing element is for adjusting a clock skew of a same stratum located one of the two of the global clock signals responsive to the phase adjustment plan.
摘要翻译： 提供了一种时钟分配网络，用于在具有两个或更多个层的3D芯片堆栈内同步全局时钟信号。 时钟分配电路在两个或更多个层中的每一个上包括相位检测器，逻辑电路和相位偏移元件。 每个相位检测器具有相应的输出，用于提供与两个或更多个层的各个不同层上的两个全局时钟信号之间的相位差有关的相位信息。 逻辑电路连接到相位检测器的相应输出端，用于确定逻辑电路响应于相位信息所位于的两个或更多个层中给定的一个给定的一个的相位调整计划。 相位去偏移元件用于响应于相位调整方案来调整位于两个全球时钟信号之一的同一层的时钟偏移。
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公开(公告)号：US20150295736A1
公开(公告)日：2015-10-15
申请号：US14669225
申请日：2015-03-26
CPC分类号： H04L25/03057 , H04B1/123 , H04L25/03063 , H04L25/03885
摘要： A continuous-time linear equalizer for use in a receiving unit of a high-speed data transmission system for receiving an input signal includes a signal line configured to provide an equalized output voltage, and an active peaking control unit, including a predetermined first number of active peaking transistors each coupled between the signal line and a power supply rail; a peaking resistor that couples gate terminals of each of the active peaking transistors to the signal line; and a first number of first setting switches each associated with each of the first number of active peaking transistors to activate a predetermined number of the first number of transistors according to first setting signals.
摘要翻译： 在用于接收输入信号的高速数据传输系统的接收单元中使用的连续时间线性均衡器包括被配置为提供均衡的输出电压的信号线以及有效峰值控制单元，其包括预定的第一数量的 每个耦合在信号线和电源轨之间的有源峰值晶体管; 峰值电阻器，其将每个有源峰值晶体管的栅极端子耦合到信号线; 以及第一数量的第一设置开关，每个与第一数量的有效峰值晶体管中的每一个相关联，以根据第一设置信号激活预定数量的第一数量的晶体管。
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公开(公告)号：US09154159B2
公开(公告)日：2015-10-06
申请号：US14144743
申请日：2013-12-31
发明人： Yong Liu
CPC分类号： H03M9/00 , H03K3/0372
摘要： A deserializer includes an input interface configured to receive an N-bit serialized stream at a source clock frequency; a modified-tree deserializing architecture that receives the first N−1 bits of the serialized stream from the input interface and generates N−1 parallel outputs corresponding to the first N−1 bits; and a last-bit flip-flop that directly samples the input interface to obtain an Nth bit, such that all N bits are available within one source clock cycle after the Nth bit arrives at the input interface.
摘要翻译： 解串器包括被配置为以源时钟频率接收N位串行化流的输入接口; 修改树反序列化架构，其从输入接口接收串行化流的第一N-1位，并产生对应于第一N-1位的N-1个并行输出; 以及直接采样输入接口以获得第N位的最后位触发器，使得在第N位到达输入接口之后，所有N位在一个源时钟周期内可用。
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公开(公告)号：US20150188567A1
公开(公告)日：2015-07-02
申请号：US14144743
申请日：2013-12-31
发明人： Yong Liu
CPC分类号： H03M9/00 , H03K3/0372
摘要： A deserializer includes an input interface configured to receive an N-bit serialized stream at a source clock frequency; a modified-tree deserializing architecture that receives the first N−1 bits of the serialized stream from the input interface and generates N−1 parallel outputs corresponding to the first N−1 bits; and a last-bit flip-flop that directly samples the input interface to obtain an Nth bit, such that all N bits are available within one source clock cycle after the Nth bit arrives at the input interface.
摘要翻译： 解串器包括被配置为以源时钟频率接收N位串行化流的输入接口; 修改树反序列化架构，其从输入接口接收串行化流的第一N-1位，并产生对应于第一N-1位的N-1个并行输出; 以及直接采样输入接口以获得第N位的最后位触发器，使得在第N位到达输入接口之后，所有N位在一个源时钟周期内可用。
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公开(公告)号：US10810487B2
公开(公告)日：2020-10-20
申请号：US15243792
申请日：2016-08-22
发明人： Bernard V. Brezzo , Leland Chang , Steven K. Esser , Daniel J. Friedman , Yong Liu , Dharmendra S. Modha , Robert K. Montoye , Bipin Rajendran , Jae-sun Seo , Jose A. Tierno
摘要： A reconfigurable neural network circuit is provided. The reconfigurable neural network circuit comprises an electronic synapse array including multiple synapses interconnecting a plurality of digital electronic neurons. Each neuron comprises an integrator that integrates input spikes and generates a signal when the integrated inputs exceed a threshold. The circuit further comprises a control module for reconfiguring the synapse array. The control module comprises a global final state machine that controls timing for operation of the circuit, and a priority encoder that allows spiking neurons to sequentially access the synapse array.
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公开(公告)号：US20160358067A1
公开(公告)日：2016-12-08
申请号：US15243792
申请日：2016-08-22
发明人： Bernard V. Brezzo , Leland Chang , Steven K. Esser , Daniel J. Friedman , Yong Liu , Dharmendra S. Modha , Robert K. Montoye , Bipin Rajendran , Jae-sun Seo , Jose A. Tierno
摘要： A reconfigurable neural network circuit is provided. The reconfigurable neural network circuit comprises an electronic synapse array including multiple synapses interconnecting a plurality of digital electronic neurons. Each neuron comprises an integrator that integrates input spikes and generates a signal when the integrated inputs exceed a threshold. The circuit further comprises a control module for reconfiguring the synapse array. The control module comprises a global final state machine that controls timing for operation of the circuit, and a priority encoder that allows spiking neurons to sequentially access the synapse array.
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公开(公告)号：US09467313B2
公开(公告)日：2016-10-11
申请号：US14745533
申请日：2015-06-22
CPC分类号： H04L25/03057 , H04B1/123 , H04L25/03063 , H04L25/03885
摘要： A continuous-time linear equalizer for use in a receiving unit of a high-speed data transmission system for receiving an input signal includes a signal line configured to provide an equalized output voltage, and an active peaking control unit, including a predetermined first number of active peaking transistors each coupled between the signal line and a power supply rail; a peaking resistor that couples gate terminals of each of the active peaking transistors to the signal line; and a first number of first setting switches each associated with each of the first number of active peaking transistors to activate a predetermined number of the first number of transistors according to first setting signals.
摘要翻译： 在用于接收输入信号的高速数据传输系统的接收单元中使用的连续时间线性均衡器包括被配置为提供均衡的输出电压的信号线以及有效峰值控制单元，其包括预定的第一数量的 每个耦合在信号线和电源轨之间的有源峰值晶体管; 峰值电阻器，其将每个有源峰值晶体管的栅极端子耦合到信号线; 以及第一数量的第一设置开关，每个与第一数量的有效峰值晶体管中的每一个相关联，以根据第一设置信号激活预定数量的第一数量的晶体管。
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