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22 条记录 (耗时 0.02 秒)

    RECONFIGURABLE AND CUSTOMIZABLE GENERAL-PURPOSE CIRCUITS FOR NEURAL NETWORKS
    3.
    发明申请
    RECONFIGURABLE AND CUSTOMIZABLE GENERAL-PURPOSE CIRCUITS FOR NEURAL NETWORKS 审中-公开
    神经网络可重构和可定制的一般用途电路

    公开(公告)号：US20160292569A1

    公开(公告)日：2016-10-06

    申请号：US15182485

    申请日：2016-06-14

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Bernard V. Brezzo ,  Leland Chang ,  Steven K. Esser ,  Daniel J. Friedman ,  Yong Liu ,  Dharmendra S. Modha ,  Robert K. Montoye ,  Bipin Rajendran ,  Jae-sun Seo ,  Jose A. Tierno

    IPC分类号： G06N3/08 ,  G06N3/04

    CPC分类号： G06N3/063 ,  G06N3/04 ,  G06N3/049 ,  G06N3/082

    摘要： A reconfigurable neural network circuit is provided. The reconfigurable neural network circuit comprises an electronic synapse array including multiple synapses interconnecting a plurality of digital electronic neurons. Each neuron comprises an integrator that integrates input spikes and generates a signal when the integrated inputs exceed a threshold. The circuit further comprises a control module for reconfiguring the synapse array. The control module comprises a global final state machine that controls timing for operation of the circuit, and a priority encoder that allows spiking neurons to sequentially access the synapse array.

    摘要翻译： 提供可重构神经网络电路。 可重构神经网络电路包括电子突触阵列，其包括互连多个数字电子神经元的多个突触。 每个神经元包括积分器，其对输入尖峰进行积分，并且当集成输入超过阈值时产生信号。 电路还包括用于重新配置突触阵列的控制模块。 控制模块包括控制电路操作的定时的全局最终状态机，以及允许加标神经元依次访问突触阵列的优先编码器。

    Phase change memory management
    4.
    发明授权
    Phase change memory management 有权
    相变记忆管理

    公开(公告)号：US09047938B2

    公开(公告)日：2015-06-02

    申请号：US13775281

    申请日：2013-02-25

    申请人： International Business Machines Corporation

    发明人： Mukta G. Farooq ,  Eren Kursun ,  Gary W. Maier ,  Bipin Rajendran

    IPC分类号： G11C7/00 ,  G11C13/00 ,  G11C7/04

    CPC分类号： G11C13/0004 ,  G11C7/04 ,  G11C13/0069 ,  G11C2213/71

    摘要： A three dimensional (3D) stack of phase change memory (PCM) devices which includes PCM devices stacked in a 3D array, the PCM devices having memory regions; a memory management unit on at least one of the PCM devices; a stack controller in the memory management unit to monitor an ambient device temperature (Tambient) with respect to a neighborhood of memory regions in the PCM devices and to adjust a programming current with respect to at least one of the memory regions in the neighborhood of memory regions in accordance with the Tambient. Also disclosed is a method of programming a PCM device.

    摘要翻译： 包括堆叠在3D阵列中的PCM设备的相变存储器（PCM）设备的三维（3D）堆叠，所述PCM设备具有存储区域; 至少一个PCM设备上的存储器管理单元; 存储器管理单元中的堆栈控制器，用于相对于PCM设备中的存储器区域的附近监测环境设备温度（Tambient），并且相对于存储器附近的至少一个存储器区域来调整编程电流 区域按照Tambient。 还公开了一种对PCM设备进行编程的方法。

    Reconfigurable and customizable general-purpose circuits for neural networks
    6.
    发明授权
    Reconfigurable and customizable general-purpose circuits for neural networks 有权
    可重构和可定制的神经网络通用电路

    公开(公告)号：US09460383B2

    公开(公告)日：2016-10-04

    申请号：US14475409

    申请日：2014-09-02

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Bernard V. Brezzo ,  Leland Chang ,  Steven K. Esser ,  Daniel J. Friedman ,  Yong Liu ,  Dharmendra S. Modha ,  Robert K. Montoye ,  Bipin Rajendran ,  Jae-sun Seo ,  Jose A. Tierno

    IPC分类号： G06N3/063

    CPC分类号： G06N3/063 ,  G06N3/04 ,  G06N3/049 ,  G06N3/082

    摘要： A reconfigurable neural network circuit is provided. The reconfigurable neural network circuit comprises an electronic synapse array including multiple synapses interconnecting a plurality of digital electronic neurons. Each neuron comprises an integrator that integrates input spikes and generates a signal when the integrated inputs exceed a threshold. The circuit further comprises a control module for reconfiguring the synapse array. The control module comprises a global final state machine that controls timing for operation of the circuit, and a priority encoder that allows spiking neurons to sequentially access the synapse array.

    摘要翻译： 提供可重构神经网络电路。 可重构神经网络电路包括电子突触阵列，其包括互连多个数字电子神经元的多个突触。 每个神经元包括积分器，其对输入尖峰进行积分，并且当集成输入超过阈值时产生信号。 电路还包括用于重新配置突触阵列的控制模块。 控制模块包括控制电路操作的定时的全局最终状态机，以及允许加标神经元依次访问突触阵列的优先编码器。

    PRODUCING SPIKE-TIMING DEPENDENT PLASTICITY IN A NEUROMORPHIC NETWORK UTILIZING PHASE CHANGE SYNAPTIC DEVICES
    7.
    发明申请
    PRODUCING SPIKE-TIMING DEPENDENT PLASTICITY IN A NEUROMORPHIC NETWORK UTILIZING PHASE CHANGE SYNAPTIC DEVICES 有权
    在使用相位变化的同步设备的神经网络中生产依赖于时间的相对塑性

    公开(公告)号：US20160224890A1

    公开(公告)日：2016-08-04

    申请号：US14990721

    申请日：2016-01-07

    申请人： International Business Machines Corporation

    发明人： Daniel J. Friedman ,  Seongwon Kim ,  Chung H. Lam ,  Dharmendra S. Modha ,  Bipin Rajendran ,  Jose A. Tierno

    IPC分类号： G06N3/063 ,  G06N3/08 ,  G06N3/04

    CPC分类号： G06N3/06 ,  G06N3/049 ,  G06N3/063 ,  G06N3/0635 ,  G06N3/08 ,  G11C11/54 ,  G11C13/0004

    摘要： Embodiments of the invention relate to a neuromorphic network for producing spike-timing dependent plasticity. The neuromorphic network includes a plurality of electronic neurons and an interconnect circuit coupled for interconnecting the plurality of electronic neurons. The interconnect circuit includes plural synaptic devices for interconnecting the electronic neurons via axon paths, dendrite paths and membrane paths. Each synaptic device includes a variable state resistor and a transistor device with a gate terminal, a source terminal and a drain terminal, wherein the drain terminal is connected in series with a first terminal of the variable state resistor. The source terminal of the transistor device is connected to an axon path, the gate terminal of the transistor device is connected to a membrane path and a second terminal of the variable state resistor is connected to a dendrite path, such that each synaptic device is coupled between a first axon path and a first dendrite path, and between a first membrane path and said first dendrite path.

    摘要翻译： 本发明的实施例涉及一种用于产生尖峰时序相关可塑性的神经形态网络。 神经元网络包括多个电子神经元和耦合用于互连多个电子神经元的互连电路。 互连电路包括用于经由轴突路径，枝晶路径和膜路径互连电子神经元的多个突触装置。 每个突触装置包括可变状态电阻器和具有栅极端子，源极端子和漏极端子的晶体管器件，其中漏极端子与可变状态电阻器的第一端子串联连接。 晶体管器件的源极端子连接到轴突路径，晶体管器件的栅极端子连接到膜路径，并且可变状态电阻器的第二端子连接到树突路径，使得每个突触器件被耦合 在第一轴突路径和第一枝晶路径之间以及在第一膜路径和所述第一枝晶路径之间。

    Global timing generator
    9.
    发明授权
    Global timing generator 有权

    公开(公告)号：US10579092B2

    公开(公告)日：2020-03-03

    申请号：US15340401

    申请日：2016-11-01

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Daniel J. Friedman ,  Seongwon Kim ,  Bipin Rajendran

    IPC分类号： G06F1/08 ,  G06N3/04 ,  G06N3/063

    摘要： Aspects include a method for generating a signal in response to an event. The method includes receiving, from a clock signal generator, a clock signal, wherein the clock signal has a fixed clock period. The method further includes receiving an indication of a pulse and, responsive to receiving the indication of the pulse, generating an output comprising a high voltage having a starting time and an ending time. The starting time is a first time when the indication of the asynchronous event is received, and the ending time is a second time at one fixed clocked period from the starting time.