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公开(公告)号：US11177167B2
公开(公告)日：2021-11-16
申请号：US15150961
申请日：2016-05-10
发明人： Daniel Edelstein , Alfred Grill , Seth L. Knupp , Son Nguyen , Takeshi Nogami , Vamsi K. Paruchuri , Hosadurga K. Shobha , Chih-Chao Yang
IPC分类号： H01L21/768 , H01L23/532 , H01L21/285 , C23C16/18 , C23C16/16 , C23C16/06 , C23C16/30 , C23C16/56 , H01L23/522 , H01L23/528 , C23C16/455 , C23C16/54 , C23C16/04 , C23C16/505
摘要： Compositions of matter, compounds, articles of manufacture and processes to reduce or substantially eliminate EM and/or stress migration, and/or TDDB in copper interconnects in microelectronic devices and circuits, especially a metal liner around copper interconnects comprise an ultra thin layer or layers of Mn alloys containing at least one of W and/or Co on the metal liner. This novel alloy provides EM and/or stress migration resistance, and/or TDDB resistance in these copper interconnects, comparable to thicker layers of other alloys found in substantially larger circuits and allows the miniaturization of the circuit without having to use thicker EM and/or TDDB resistant alloys previously used thereby enhancing the miniaturization, i.e., these novel alloy layers can be miniaturized along with the circuit and provide substantially the same EM and/or TDDB resistance as thicker layers of different alloy materials previously used that lose some of their EM and/or TDDB resistance when used as thinner layers.
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公开(公告)号：US10157789B2
公开(公告)日：2018-12-18
申请号：US15239178
申请日：2016-08-17
发明人： Shyng-Tsong Chen , Cheng Chi , Chi-Chun Liu , Sylvie M. Mignot , Yann A. Mignot , Hosadurga K. Shobha , Terry A. Spooner , Wenhui Wang , Yongan Xu
IPC分类号： H01L21/768 , H01L23/485 , H01L23/522 , H01L23/528 , H01L23/532
摘要： A method of forming a via to an underlying layer of a semiconductor device is provided. The method may include forming a pillar over the underlying layer using a sidewall image transfer process. A dielectric layer is formed over the pillar and the underlying layer; and a via mask patterned over the dielectric layer, the via mask having a mask opening at least partially overlapping the pillar. A via opening is etched in the dielectric layer using the via mask, the mask opening defining a first lateral dimension of the via opening in a first direction and the pillar defining a second lateral dimension of the via opening in a second direction different than the first direction. The via opening is filled with a conductor to form the via. A semiconductor device and via structure are also provided.
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3.发明申请VIA FORMATION USING SIDEWALL IMAGE TRANSFER PROCESS TO DEFINE LATERAL DIMENSION 有权通过使用边框图像转移过程来形成侧向尺寸公开(公告)号：US20160336225A1
公开(公告)日：2016-11-17
申请号：US14710894
申请日：2015-05-13
发明人： Shyng-Tsong Chen , Cheng Chi , Chi-Chun Liu , Sylvie M. Mignot , Yann A. Mignot , Hosadurga K. Shobha , Terry A. Spooner , Wenhui Wang , Yongan Xu
IPC分类号： H01L21/768 , H01L23/528 , H01L23/535
CPC分类号： H01L21/76897 , H01L21/76802 , H01L21/76811 , H01L21/76816 , H01L21/76829 , H01L21/76834 , H01L21/76885 , H01L23/485 , H01L23/5226 , H01L23/5283 , H01L23/53238 , H01L23/53266 , H01L23/5329
摘要： A method of forming a via to an underlying layer of a semiconductor device is provided. The method may include forming a pillar over the underlying layer using a sidewall image transfer process. A dielectric layer is formed over the pillar and the underlying layer; and a via mask patterned over the dielectric layer, the via mask having a mask opening at least partially overlapping the pillar. A via opening is etched in the dielectric layer using the via mask, the mask opening defining a first lateral dimension of the via opening in a first direction and the pillar defining a second lateral dimension of the via opening in a second direction different than the first direction. The via opening is filled with a conductor to form the via. A semiconductor device and via structure are also provided.
摘要翻译： 提供了形成通孔到半导体器件的下层的方法。 该方法可以包括使用侧壁图像转移过程在下层上形成柱。 介电层形成在柱和下层之上; 以及图案化在所述电介质层上的通孔掩模，所述通孔掩模具有至少部分地与所述支柱重叠的掩模开口。 使用通孔掩模在电介质层中蚀刻通孔开口，掩模开口在第一方向上限定通孔开口的第一横向尺寸，并且柱沿不同于第一方向的第二方向限定通孔开口的第二横向尺寸 方向。 通孔开口填充有导体以形成通孔。 还提供了半导体器件和通孔结构。
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公开(公告)号：US08981466B2
公开(公告)日：2015-03-17
申请号：US13792374
申请日：2013-03-11
发明人： Alfred Grill , Seth L. Knupp , Son V. Nguyen , Vamsi K. Paruchuri , Deepika Priyadarshini , Hosadurga K. Shobha
IPC分类号： H01L21/283 , H01L21/3115 , H01L21/473 , H01L21/02 , H01L29/66 , H01L29/78
CPC分类号： H01L21/02126 , H01L21/0214 , H01L21/02164 , H01L21/0217 , H01L21/022 , H01L21/02247 , H01L21/02274 , H01L21/0228 , H01L21/02326 , H01L21/02329 , H01L21/0234 , H01L21/76283 , H01L21/76831 , H01L21/76832 , H01L21/76834 , H01L23/481 , H01L29/665 , H01L29/6656 , H01L29/7833 , H01L29/7843 , H01L2924/0002 , H01L2924/00
摘要： Multilayer dielectric structures are provided having silicon nitride (SiN) and silicon oxynitride (SiNO) films for use as capping layers, liners, spacer barrier layers, and etch stop layers, and other components of semiconductor nano-devices. For example, a semiconductor structure includes a multilayer dielectric structure having multiple layers of dielectric material including one or more SiN layers and one or more SiNO layers. The layers of dielectric material in the multilayer dielectric structure have a thickness in a range of about 0.5 nanometers to about 3 nanometers.
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公开(公告)号：US10325806B2
公开(公告)日：2019-06-18
申请号：US15825646
申请日：2017-11-29
发明人： Daniel C. Edelstein , Son V. Nguyen , Takeshi Nogami , Deepika Priyadarshini , Hosadurga K. Shobha
IPC分类号： H01L21/768 , H01L23/528 , H01L23/532 , H01L23/522 , H01L21/02
摘要： Low capacitance and high reliability interconnect structures and methods of manufacture are disclosed. The method includes forming a copper based interconnect structure in an opening of a dielectric material. The method further includes forming a capping layer on the copper based interconnect structure. The method further includes oxidizing the capping layer and any residual material formed on a surface of the dielectric material. The method further includes forming a barrier layer on the capping layer by outdiffusing a material from the copper based interconnect structure to a surface of the capping layer. The method further includes removing the residual material, while the barrier layer on the surface of the capping layer protects the capping layer.
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6.发明申请VIA FORMATION USING SIDEWALL IMAGE TRANFER PROCESS TO DEFINE LATERAL DIMENSION 审中-公开通过使用边框图像平移过程确定横向尺寸的形式公开(公告)号：US20160358820A1
公开(公告)日：2016-12-08
申请号：US15239178
申请日：2016-08-17
发明人： Shyng-Tsong Chen , Cheng Chi , Chi-Chun Liu , Sylvie M. Mignot , Yann A. Mignot , Hosadurga K. Shobha , Terry A. Spooner , Wenhui Wang , Yongan Xu
IPC分类号： H01L21/768 , H01L23/522 , H01L23/528 , H01L23/532
CPC分类号： H01L21/76897 , H01L21/76802 , H01L21/76811 , H01L21/76816 , H01L21/76829 , H01L21/76834 , H01L21/76885 , H01L23/485 , H01L23/5226 , H01L23/5283 , H01L23/53238 , H01L23/53266 , H01L23/5329
摘要： A method of forming a via to an underlying layer of a semiconductor device is provided. The method may include forming a pillar over the underlying layer using a sidewall image transfer process. A dielectric layer is formed over the pillar and the underlying layer; and a via mask patterned over the dielectric layer, the via mask having a mask opening at least partially overlapping the pillar. A via opening is etched in the dielectric layer using the via mask, the mask opening defining a first lateral dimension of the via opening in a first direction and the pillar defining a second lateral dimension of the via opening in a second direction different than the first direction. The via opening is filled with a conductor to form the via. A semiconductor device and via structure are also provided.
摘要翻译： 提供了形成通孔到半导体器件的下层的方法。 该方法可以包括使用侧壁图像转移过程在下层上形成柱。 介电层形成在柱和下层之上; 以及图案化在所述电介质层上的通孔掩模，所述通孔掩模具有至少部分地与所述支柱重叠的掩模开口。 使用通孔掩模在电介质层中蚀刻通孔开口，掩模开口在第一方向上限定通孔开口的第一横向尺寸，并且柱沿不同于第一方向的第二方向限定通孔开口的第二横向尺寸 方向。 通孔开口填充有导体以形成通孔。 还提供了半导体器件和通孔结构。
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公开(公告)号：US09449810B2
公开(公告)日：2016-09-20
申请号：US14847350
申请日：2015-09-08
IPC分类号： H01L21/47 , H01L21/02 , H01B3/46 , H01L23/532
CPC分类号： H01L21/02126 , H01B3/46 , H01L21/02203 , H01L21/02211 , H01L21/02216 , H01L21/02274 , H01L21/0234 , H01L21/02348
摘要： Disclosed herein is an ultra-low dielectric (k) film and methods of making thereof. A ultra-low k film has a covalently bonded network comprising atoms of silicon, oxygen, carbon, and hydrogen, a cyclotrisilane structure, and a plurality of pores having a pore size distribution (PSD) of less than about 1.1 nanometers (nm). The ultra-low k film has a k value of less than about 2.4 and at least about 28 atomic percent of carbon.
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8.发明授权Advanced ultra low k SiCOH dielectrics prepared by built-in engineered pore size and bonding structured with cyclic organosilicon precursors 有权通过内置工程孔径和用循环有机硅前体结构的键合制备的先进的超低k SiCOH电介质公开(公告)号：US09209017B2
公开(公告)日：2015-12-08
申请号：US14225810
申请日：2014-03-26
IPC分类号： H01L21/47 , H01L21/02 , H01B3/46 , H01L23/532
CPC分类号： H01L21/02126 , H01B3/46 , H01L21/02203 , H01L21/02211 , H01L21/02216 , H01L21/02274 , H01L21/0234 , H01L21/02348
摘要： Disclosed herein is an ultra-low dielectric (k) film and methods of making thereof. A ultra-low k film has a covalently bonded network comprising atoms of silicon, oxygen, carbon, and hydrogen, a cyclotrisilane structure, and a plurality of pores having a pore size distribution (PSD) of less than about 1.1 nanometers (nm). The ultra-low k film has a k value of less than about 2.4 and at least about 28 atomic percent of carbon.
摘要翻译： 本文公开了一种超低介电（k）薄膜及其制造方法。 超低k膜具有包含硅，氧，碳和氢的原子，环状硅烷结构和孔径分布（PSD）小于约1.1纳米（nm）的多个孔的共价键合网络。 超低k膜具有小于约2.4的k值和至少约28原子％的碳。
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9.发明申请公开(公告)号：US20140179119A1
公开(公告)日：2014-06-26
申请号：US14194036
申请日：2014-02-28
IPC分类号： H01L21/02
CPC分类号： H01L21/02263 , C23C16/325 , C23C16/56 , H01L21/76825 , H01L21/76826 , H01L21/76829 , H01L21/76832 , H01L21/76834
摘要： A method of forming a carbon-rich silicon carbide-like dielectric film having a carbon concentration of greater than, or equal to, about 30 atomic % C and a dielectric constant of less than, or equal to, about 4.5 is provided. The dielectric film may optionally include nitrogen. When nitrogen is present, the carbon-rich silicon carbide-like dielectric film has a concentration nitrogen that is less than, or equal, to about 5 atomic % nitrogen.
摘要翻译： 提供了形成碳浓度大于或等于约30原子％C并且介电常数小于或等于约4.5的富碳碳化硅状电介质膜的方法。 电介质膜可以任选地包括氮。 当存在氮时，富含碳的碳化硅状电介质膜具有小于或等于约5原子％氮的浓度氮。
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公开(公告)号：US20160276216A1
公开(公告)日：2016-09-22
申请号：US15151260
申请日：2016-05-10
发明人： DANIEL EDELSTEIN , Alfred Grill , Seth L. Knupp , Son Nguyen , Takeshi Nogami , Vamsi K. Paruchuri , Hosadurga K. Shobha , Chih-Chao Yang
IPC分类号： H01L21/768 , H01L23/532 , C23C16/30 , C23C16/56 , C23C16/455 , H01L23/522 , C23C16/06
CPC分类号： H01L21/76843 , C23C16/04 , C23C16/06 , C23C16/16 , C23C16/18 , C23C16/30 , C23C16/45525 , C23C16/45544 , C23C16/505 , C23C16/54 , C23C16/56 , H01L21/28556 , H01L21/28562 , H01L21/28568 , H01L21/76802 , H01L21/76831 , H01L21/76834 , H01L21/7684 , H01L21/76846 , H01L21/76849 , H01L21/7685 , H01L21/76852 , H01L21/76862 , H01L21/76864 , H01L21/76879 , H01L21/76883 , H01L23/5226 , H01L23/528 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： Compositions of matter, compounds, articles of manufacture and processes to reduce or substantially eliminate EM and/or stress migration, and/or TDDB in copper interconnects in microelectronic devices and circuits, especially a metal liner around copper interconnects comprise an ultra thin layer or layers of Mn alloys containing at least one of W and/or Co on the metal liner. This novel alloy provides EM and/or stress migration resistance, and/or TDDB resistance in these copper interconnects, comparable to thicker layers of other alloys found in substantially larger circuits and allows the miniaturization of the circuit without having to use thicker EM and/or TDDB resistant alloys previously used thereby enhancing the miniaturization, i.e., these novel alloy layers can be miniaturized along with the circuit and provide substantially the same EM and/or TDDB resistance as thicker layers of different alloy materials previously used that lose some of their EM and/or TDDB resistance when used as thinner layers.
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