公开(公告)号：US08351215B2

公开(公告)日：2013-01-08

申请号：US12320523

申请日：2009-01-28

申请人： Hong Won Kim ,  Sung Yi ,  Tae Sung Jeong ,  Joon Seok Kang

发明人： Hong Won Kim ,  Sung Yi ,  Tae Sung Jeong ,  Joon Seok Kang

IPC分类号： H05K3/00

CPC分类号： H05K1/185 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/82 ,  H01L2224/24226 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H05K2201/0355 ,  H05K2201/0394 ,  H05K2201/10674 ,  H05K2203/1469 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49146 ,  Y10T29/49147 ,  Y10T29/49155

摘要： The present invention relates to a chip embedded printed circuit board and a manufacturing method thereof. The present invention provides the chip embedded printed circuit board including an insulating layer embedding a chip provided with posts at an upper part, vias formed through the insulating layer, upper patterns formed at the upper part of the insulating layer to be connected to the posts and the vias and lower patterns formed at a lower part of the insulating layer to be connected to the vias, and the manufacturing method thereof.

摘要翻译： 芯片嵌入式印刷电路板及其制造方法技术领域本发明涉及一种嵌入式芯片的印刷电路板及其制造方法。 本发明提供了一种芯片嵌入式印刷电路板，其包括嵌入在上部设置有柱的芯片的绝缘层，通过绝缘层形成的通孔，形成在要连接到柱的绝缘层的上部的上部图案， 形成在绝缘层的与通孔连接的下部的通孔和下部图案及其制造方法。

公开(公告)号：US08893380B2

公开(公告)日：2014-11-25

申请号：US12320492

申请日：2009-01-27

申请人： Hong Won Kim ,  Sung Yi ,  Tae Sung Jeong ,  Joon Seok Kang

发明人： Hong Won Kim ,  Sung Yi ,  Tae Sung Jeong ,  Joon Seok Kang

IPC分类号： H05K3/30 ,  H01L23/00 ,  H05K1/18 ,  H01L21/683 ,  H05K3/42

CPC分类号： H05K1/185 ,  H01L21/568 ,  H01L21/6835 ,  H01L24/18 ,  H01L24/19 ,  H01L24/82 ,  H01L24/96 ,  H01L2224/04105 ,  H01L2224/18 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01059 ,  H01L2924/01078 ,  H05K3/426 ,  H05K2201/10515 ,  H05K2201/10674 ,  H05K2203/1461 ,  Y10T29/4913 ,  Y10T29/49146 ,  Y10T29/49165

摘要： The present invention relates to a chip embedded printed circuit board and a manufacturing method thereof and provides a chip embedded printed circuit board including: an insulating layer having vias formed therethrough; a first chip and a second chip embedded in the insulating layer and having pads, which are respectively exposed to upper and lower surfaces of the insulating layer, on one surfaces thereof; an upper pattern formed on the upper surface of the insulating layer to be connected to the pads of the first chip and the vias; and a lower pattern formed on the lower surface of the insulating layer to be connected to the pads of the second chip and the vias. Also, the present invention provides a manufacturing method of a chip embedded printed circuit board.

摘要翻译： 芯片嵌入式印刷电路板及其制造方法技术领域本发明涉及一种芯片嵌入式印刷电路板及其制造方法，其特征在于，提供一种芯片嵌入式印刷电路基板， 嵌入绝缘层中的第一芯片和第二芯片，并且在其一个表面上分别暴露于绝缘层的上表面和下表面的焊盘; 形成在绝缘层的上表面上以连接到第一芯片的焊盘和通孔的上部图案; 以及形成在绝缘层的下表面上以连接到第二芯片的焊盘和通孔的下图案。 另外，本发明提供一种嵌入式芯片的印刷电路板的制造方法。

公开(公告)号：US20100142170A1

公开(公告)日：2010-06-10

申请号：US12320492

申请日：2009-01-27

申请人： Hong Won Kim ,  Sung Yi ,  Tae Sung Jeong ,  Joon Seok Kang

发明人： Hong Won Kim ,  Sung Yi ,  Tae Sung Jeong ,  Joon Seok Kang

IPC分类号： H05K1/18 ,  H05K3/30

CPC分类号： H05K1/185 ,  H01L21/568 ,  H01L21/6835 ,  H01L24/18 ,  H01L24/19 ,  H01L24/82 ,  H01L24/96 ,  H01L2224/04105 ,  H01L2224/18 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01059 ,  H01L2924/01078 ,  H05K3/426 ,  H05K2201/10515 ,  H05K2201/10674 ,  H05K2203/1461 ,  Y10T29/4913 ,  Y10T29/49146 ,  Y10T29/49165

摘要： The present invention relates to a chip embedded printed circuit board and a manufacturing method thereof and provides a chip embedded printed circuit board including: an insulating layer having vias formed therethrough; a first chip and a second chip embedded in the insulating layer and having pads, which are respectively exposed to upper and lower surfaces of the insulating layer, on one surfaces thereof; an upper pattern formed on the upper surface of the insulating layer to be connected to the pads of the first chip and the vias; and a lower pattern formed on the lower surface of the insulating layer to be connected to the pads of the second chip and the vias. Also, the present invention provides a manufacturing method of a chip embedded printed circuit board.

摘要翻译： 芯片嵌入式印刷电路板及其制造方法技术领域本发明涉及一种芯片嵌入式印刷电路板及其制造方法，其特征在于，提供一种芯片嵌入式印刷电路板，其具备：具有通孔形成的绝缘层; 嵌入绝缘层中的第一芯片和第二芯片，并且在其一个表面上分别暴露于绝缘层的上表面和下表面的焊盘; 形成在绝缘层的上表面上以连接到第一芯片的焊盘和通孔的上部图案; 以及形成在绝缘层的下表面上以连接到第二芯片的焊盘和通孔的下图案。 另外，本发明提供一种嵌入式芯片的印刷电路板的制造方法。

公开(公告)号：US20100134991A1

公开(公告)日：2010-06-03

申请号：US12320523

申请日：2009-01-28

申请人： Hong Won Kim ,  Sung Yi ,  Tae Sung Jeong ,  Joon Seok Kang

发明人： Hong Won Kim ,  Sung Yi ,  Tae Sung Jeong ,  Joon Seok Kang

IPC分类号： H05K1/18 ,  H05K3/30

CPC分类号： H05K1/185 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/82 ,  H01L2224/24226 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H05K2201/0355 ,  H05K2201/0394 ,  H05K2201/10674 ,  H05K2203/1469 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49146 ,  Y10T29/49147 ,  Y10T29/49155

摘要： The present invention relates to a chip embedded printed circuit board and a manufacturing method thereof. The prevent invention provides the chip embedded printed circuit board including an insulating layer embedding a chip provided with posts at an upper part, vias formed through the insulating layer, upper patterns formed at the upper part of the insulating layer to be connected to the posts and the vias and lower patterns formed at a lower part of the insulating layer to be connected to the vias, and the manufacturing method thereof.

摘要翻译： 芯片嵌入式印刷电路板及其制造方法技术领域本发明涉及一种嵌入式芯片的印刷电路板及其制造方法。 本发明提供了一种芯片嵌入式印刷电路板，其包括：绝缘层，其嵌入在上部设置有柱的芯片，通过绝缘层形成的通孔，形成在要连接到柱的绝缘层的上部的上部图案;以及 形成在绝缘层的与通孔连接的下部的通孔和下部图案及其制造方法。

公开(公告)号：US07632709B2

公开(公告)日：2009-12-15

申请号：US12149106

申请日：2008-04-25

申请人： Hyung-Jin Jeon ,  Sung Yi ,  Young-Do Kweon ,  Jong-Yun Lee ,  Joon-Seok Kang ,  Seung-Wook Park

发明人： Hyung-Jin Jeon ,  Sung Yi ,  Young-Do Kweon ,  Jong-Yun Lee ,  Joon-Seok Kang ,  Seung-Wook Park

IPC分类号： H01L21/00

CPC分类号： H01L23/3114 ,  H01L21/6835 ,  H01L24/11 ,  H01L24/12 ,  H01L24/24 ,  H01L24/27 ,  H01L24/82 ,  H01L2221/68372 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/16 ,  H01L2224/24227 ,  H01L2224/274 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01059 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/15153 ,  H01L2924/1517

摘要： A method of manufacturing a wafer level package is disclosed. The method may include stacking an insulation layer over a wafer substrate; processing a via hole in the insulation layer; forming a seed layer over the insulation layer; forming a plating resist, which is in a corresponding relationship with a redistribution pattern, over the seed layer; forming the redistribution pattern, which includes a terminal for external contact, by electroplating; and coupling a conductive ball to the terminal. As multiple redistribution layers can be formed using inexpensive PCB processes, the manufacturing costs can be reduced, and the stability and efficiency of the process can be increased.

公开(公告)号：US08779580B2

公开(公告)日：2014-07-15

申请号：US12010321

申请日：2008-01-23

申请人： Joon-Seok Kang ,  Sung Yi ,  Jae-Cheon Doh ,  Do-Jae Yoo ,  Sun-Kyong Kim ,  Jong-Hwan Baek

发明人： Joon-Seok Kang ,  Sung Yi ,  Jae-Cheon Doh ,  Do-Jae Yoo ,  Sun-Kyong Kim ,  Jong-Hwan Baek

IPC分类号： H01L23/10 ,  H01L23/34

CPC分类号： H05K1/0203 ,  H01L21/50 ,  H01L23/3675 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/24227 ,  H01L2224/73253 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/15153 ,  H01L2924/1517 ,  H05K2201/066 ,  Y10T29/49146

摘要： An electronic component package and a manufacturing method thereof are disclosed. The electronic component package manufacturing method, which includes mounting an electronic component in one surface of a first insulation layer; bonding a heat sink to the one surface of the first insulation layer, corresponding to the electronic component, to cover the electronic component, the heat sink being formed with a cavity; charging the cavity with an adhesive; and forming a circuit pattern in the other surface of the first insulation layer, can prevent a void from being generated in the adhesive, make the handling stable and make the size small by allowing the heat sink formed with the cavity to cover the electronic component before the pattern build-up and supplying the adhesive through one side of the cavity while providing negative pressure through the other side.

摘要翻译： 公开了一种电子部件封装及其制造方法。 电子部件封装制造方法，其包括将电子部件安装在第一绝缘层的一个表面中; 将散热器与对应于电子部件的第一绝缘层的一个表面接合以覆盖电子部件，散热器形成有空腔; 用粘合剂填充空腔; 并且在第一绝缘层的另一个表面上形成电路图案，可以防止在粘合剂中产生空隙，使得处理稳定并且通过使形成有空腔的散热器覆盖电子元件的尺寸变小， 图案积聚并通过腔的一侧供应粘合剂，同时通过另一侧提供负压。

公开(公告)号：US20090124075A1

公开(公告)日：2009-05-14

申请号：US12149014

申请日：2008-04-24

申请人： Joon-Seok Kang ,  Sung Yi ,  Jong-Hwan Baek ,  Young-Do Kweon

发明人： Joon-Seok Kang ,  Sung Yi ,  Jong-Hwan Baek ,  Young-Do Kweon

IPC分类号： H01L21/768

CPC分类号： H01L24/13 ,  H01L24/11 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05147 ,  H01L2224/05611 ,  H01L2224/11334 ,  H01L2224/1147 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/16 ,  H01L2924/00013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00

摘要： A method of manufacturing a wafer level package is disclosed, which may include: coating an insulation layer over one side of a semiconductor chip, on one side of which an electrode pad is formed, such that the electrode pad is open; forming a seed layer by depositing a conductive metal onto one side of the semiconductor chip; forming a rewiring pattern that is electrically connected with the electrode pad, by selective electroplating with the seed layer as an electrode; forming a conductive pillar that is electrically connected with the rewiring pattern, by selective electroplating with the seed layer as an electrode; and removing portions of the seed layer open to the exterior. By forming the rewiring pattern and the metal pillar using one seed layer, the manufacturing process can be simplified, whereby defects during the manufacturing process can be reduced and the reliability of the products can be improved.

摘要翻译： 公开了一种制造晶片级封装的方法，其可以包括：在半导体芯片的一侧上涂覆绝缘层，其一面形成电极焊盘，使得电极焊盘打开; 通过在所述半导体芯片的一侧上沉积导电金属形成晶种层; 形成与电极焊盘电连接的重新布线图案，通过选择性地电镀种子层作为电极; 形成与所述重新布线图案电连接的导电柱，通过所述种子层作为电极的选择性电镀; 并将种子层的部分去除到外部。 通过使用一个种子层形成再布线图案和金属柱，可以简化制造工艺，从而可以减少制造过程中的缺陷，并且可以提高产品的可靠性。

公开(公告)号：US20120129297A1

公开(公告)日：2012-05-24

申请号：US13363513

申请日：2012-02-01

申请人： Joon Seok KANG ,  Sung Yi ,  Young Do Kweon

发明人： Joon Seok KANG ,  Sung Yi ,  Young Do Kweon

IPC分类号： H01L21/78

CPC分类号： H01L23/3114 ,  H01L21/56 ,  H01L21/568 ,  H01L24/19 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2224/82 ,  H01L2924/00

摘要： A method of manufacturing a wafer level package including: separating chips by dicing a wafer; forming a removable resin layer in a space between the separated chips and at upper parts thereof; separating the chips by dicing the removable resin layer; mounting the chips separated in a state of being surrounded by the removable resin layer, on a carrier plate; forming a molding material on the carrier plate to cover the removable resin layer; separating the carrier plate from the chips; forming a dielectric layer having redistribution lines connected to the chips, on the chips exposed by separating the carrier plate; and forming a solder resist layer on the dielectric layer to expose portions of the redistribution lines.

摘要翻译： 一种制造晶片级封装的方法，包括：通过切割晶片来分离芯片; 在分离的碎片之间的空间中和在其上部形成可移除的树脂层; 通过切割可去除的树脂层来分离芯片; 将被分离的芯片安装在可移除树脂层周围的状态下; 在载体板上形成模塑材料以覆盖可除去的树脂层; 将载板与芯片分离; 在通过分离载体板而暴露的芯片上形成具有连接到芯片的再分配线的电介质层; 以及在所述电介质层上形成阻焊层以暴露所述再分配线的部分。

公开(公告)号：US08110914B2

公开(公告)日：2012-02-07

申请号：US12318752

申请日：2009-01-07

申请人： Joon Seok Kang ,  Sung Yi ,  Young Do Kweon

发明人： Joon Seok Kang ,  Sung Yi ,  Young Do Kweon

IPC分类号： H01L23/498 ,  H01L21/78

CPC分类号： H01L23/3114 ,  H01L21/56 ,  H01L21/568 ,  H01L24/19 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2224/82 ,  H01L2924/00

摘要： A wafer level package includes a chip, a removable resin layer, a molding material, a dielectric layer, redistribution lines and a solder resist. The removable resin layer is formed to surround side surfaces and a lower surface of the chip. The molding material is formed on the lower surface of the removable resin layer. The dielectric layer is formed over the removable resin layer including the chip and having via holes to expose portions of the chip. The redistribution lines are formed on the dielectric layer including insides of the via holes to be connected to the chip. The solder resist layer is formed on the dielectric layer to expose portions of the redistribution lines.

摘要翻译： 晶片级封装包括芯片，可移除树脂层，成型材料，电介质层，再分布线和阻焊剂。 可移除树脂层形成为围绕芯片的侧表面和下表面。 成型材料形成在可移除树脂层的下表面上。 电介质层形成在包括芯片的可移除树脂层上，并且具有通孔以暴露芯片的部分。 再分配线形成在包括要连接到芯片的通孔的内部的电介质层上。 在电介质层上形成阻焊层以暴露再分布线的部分。

公开(公告)号：US20100193932A1

公开(公告)日：2010-08-05

申请号：US12424514

申请日：2009-04-15

申请人： Joon Seok KANG ,  Sung Yi ,  Young Do Kweon

发明人： Joon Seok KANG ,  Sung Yi ,  Young Do Kweon

IPC分类号： H01L23/48 ,  H01L21/78

CPC分类号： H01L23/5389 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/4334 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05548 ,  H01L2224/12105 ,  H01L2924/00014 ,  H01L2924/01012 ,  H01L2924/01073 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/05599

摘要： Disclosed herein are a wafer level package for heat dissipation and a method of manufacturing the same. The wafer level package includes a heat dissipation plate including a cavity and a hole, a die including a pad disposed in the cavity of the heat dissipation plate in a face-up manner, a thermal conductive adhesive disposed between the die and an inner wall of the cavity and disposed in the hole, and a redistribution layer connected at one end to the pad and at the other end extended. The wafer level package protects the die from external environments and enables the die to be easily flush with the heat dissipation plate.

摘要翻译： 这里公开了用于散热的晶片级封装及其制造方法。 晶片级封装包括包括空腔和孔的散热板，包括以面朝上的方式设置在散热板的空腔中的焊盘的模具，设置在模具和内壁之间的导热粘合剂 空腔并设置在孔中，并且再分配层在一端连接到垫并且在另一端延伸。 晶圆级封装保护模具免受外部环境的影响，使模具能够轻松地与散热板齐平。