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    Redundant memory cell selecting circuit having fuses coupled to memory cell group address and memory cell block address
    2.
    发明授权
    Redundant memory cell selecting circuit having fuses coupled to memory cell group address and memory cell block address 失效
    冗余存储单元选择电路具有耦合到存储单元组地址和存储单元块地址的熔丝

    公开(公告)号：US5953264A

    公开(公告)日：1999-09-14

    申请号：US937006

    申请日：1997-09-24

    申请人： Hiroshige Hirano ,  Hisakazu Kotani ,  Naomi Miyake

    发明人： Hiroshige Hirano ,  Hisakazu Kotani ,  Naomi Miyake

    IPC分类号： G11C29/00 ,  G11C29/24 ,  G11C13/00

    CPC分类号： G11C29/808 ,  G11C29/24 ,  G11C29/812 ,  G11C29/844

    摘要： An apparatus for selecting redundant memory cells in integrated circuit memory devices. The apparatus includes eight memory cell blocks, each of which includes a plurality of memory cell groups, a redundant memory cell group of a first set and a redundant memory cell group of a second set; and eight selecting fuse circuit blocks. Four of the selecting fuse circuit blocks are coupled to the memory cell blocks and adapted to select a redundant word line group of the first set of any of the eight memory cell blocks, and the other four selecting fuse circuit blocks are coupled to the memory cell blocks and adapted to select a redundant word line group of the second set of any of the eight memory cell blocks.

    摘要翻译： 一种用于在集成电路存储器件中选择冗余存储单元的装置。 该装置包括八个存储单元块，每个存储单元块包括多个存储单元组，第一组的冗余存储单元组和第二组的冗余存储单元组; 和八个选择熔丝电路块。 选择熔丝电路块中的四个耦合到存储单元块并且适于选择八个存储单元块中的任一个的第一组的冗余字线组，而另外四个选择熔丝电路块耦合到存储单元 并且适于选择八个存储器单元块中的任何一个的第二组的冗余字线组。

    Semiconductor device
    4.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US08710667B2

    公开(公告)日：2014-04-29

    申请号：US13289683

    申请日：2011-11-04

    申请人： Hiroshige Hirano ,  Yukitoshi Ota

    发明人： Hiroshige Hirano ,  Yukitoshi Ota

    IPC分类号： H01L23/48

    CPC分类号： H01L23/522 ,  H01L23/528 ,  H01L23/5286 ,  H01L27/0203 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device includes a first interconnect layer and a second interconnect layer provided above or under the first interconnect layer. The first interconnect layer includes a plurality of first interconnect blocks, and in each of the first interconnect blocks, a first interconnect has a first potential, and extends in at least two or more directions, and a second interconnect has a second potential, and extends in at least two or more directions. The second interconnect layer includes a third interconnect which electrically connects the first interconnect of one of a pair of adjacent first interconnect blocks and the first interconnect of the other of the pair of adjacent first interconnect blocks, and a fourth interconnect which electrically connects the second interconnect of one of the pair of adjacent first interconnect blocks and the second interconnect of the other of the pair of adjacent first interconnect blocks.

    摘要翻译： 半导体器件包括设置在第一互连层上方或下方的第一互连层和第二互连层。 第一互连层包括多个第一互连块，并且在每个第一互连块中，第一互连具有第一电位，并且在至少两个或更多个方向上延伸，并且第二互连具有第二电位，并且延伸 在至少两个或更多个方向。 第二互连层包括第三互连，其将一对相邻的第一互连块中的一个的第一互连与该对相邻的第一互连块中的另一个的第一互连电连接，以及将第二互连电连接的第四互连 所述一对相邻的第一互连块中的一个和所述一对相邻的第一互连块中的另一个的所述第二互连。

    SEMICONDUCTOR DEVICE HAVING SEAL WIRING
    5.
    发明申请
    SEMICONDUCTOR DEVICE HAVING SEAL WIRING 有权
    具有密封接线的半导体器件

    公开(公告)号：US20120181670A1

    公开(公告)日：2012-07-19

    申请号：US13428992

    申请日：2012-03-23

    申请人： Koji TAKEMURA ,  Hiroshige Hirano ,  Yutaka Itoh ,  Hikari Sano ,  Koji Koike

    发明人： Koji TAKEMURA ,  Hiroshige Hirano ,  Yutaka Itoh ,  Hikari Sano ,  Koji Koike

    IPC分类号： H01L23/00

    CPC分类号： H01L23/585 ,  H01L23/562 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device includes: an interlayer insulating film formed on a substrate; a wiring formed in the interlayer insulating film in a chip region of the substrate; a seal ring formed in the interlayer insulating film in a periphery of the chip region and continuously surrounding the chip region; and a first protective film formed on the interlayer insulating film having the wiring and the seal ring formed therein. A first opening is formed in the first protective film in a region located outside the seal ring when viewed from the chip region, and the interlayer insulating film is exposed in the first opening.

    摘要翻译： 半导体器件包括：形成在衬底上的层间绝缘膜; 在衬底的芯片区域中的层间绝缘膜中形成的布线; 密封环，形成在所述芯片区域的周围的所述层间绝缘膜中，并且连续地围绕所述芯片区域; 以及形成在其上形成有布线和密封环的层间绝缘膜上的第一保护膜。 当从芯片区域观察时，在位于密封环外侧的区域中的第一保护膜中形成第一开口，并且层间绝缘膜在第一开口中露出。

    Semiconductor memory device
    7.
    再颁专利
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：USRE41879E1

    公开(公告)日：2010-10-26

    申请号：US12155392

    申请日：2008-06-03

    申请人： Shunichi Iwanari ,  Masahiko Sakagami ,  Hiroshige Hirano ,  Tetsuji Nakakuma ,  Takashi Miki ,  Yasushi Gohou ,  Kunisato Yamaoka ,  Yasuo Murakuki

    发明人： Shunichi Iwanari ,  Masahiko Sakagami ,  Hiroshige Hirano ,  Tetsuji Nakakuma ,  Takashi Miki ,  Yasushi Gohou ,  Kunisato Yamaoka ,  Yasuo Murakuki

    IPC分类号： G11C16/06

    CPC分类号： G11C11/4076 ,  G11C7/1051 ,  G11C7/1063 ,  G11C2207/229

    摘要： Provided is a semiconductor memory device compatible with a SRAM and capable of a high-speed data transfer operation while maintaining data reliability. An access to a memory core 6 starts when an external chip enable signal XCE performs a falling transition. Simultaneously, an external write enable signal XWE and an external address signal ADD are received, and a memory cell 1, in the memory core 6, corresponding to the received external address signal ADD is selected. When a data read-out from the memory cell 1 or a data write-in to the memory cell 1 is complete, a rewrite timer 7 is activated in accordance with a rising transition of an external chip enable signal XCE or a rising transition of the external write enable signal XWE for performing a data rewrite for the memory cell 1.

    摘要翻译： 提供了与SRAM兼容的半导体存储器件，并且能够在保持数据可靠性的同时进行高速数据传输操作。 当外部芯片使能信号XCE执行下降转换时，对存储器核心6的访问开始。 同时，接收外部写入使能信号XWE和外部地址信号ADD，并且选择与存储器核心6中对应于所接收的外部地址信号ADD的存储单元1。 当从存储器单元1读出的数据或对存储器单元1的数据写入完成时，根据外部芯片使能信号XCE的上升转变或者上升沿的转换激活重写定时器7 用于对存储单元1执行数据重写的外部写使能信号XWE。

    Semiconductor device
    8.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US07538433B2

    公开(公告)日：2009-05-26

    申请号：US11452957

    申请日：2006-06-15

    申请人： Koji Takemura ,  Hiroshige Hirano ,  Yutaka Itoh ,  Hikari Sano ,  Masao Takahashi ,  Koji Koike

    发明人： Koji Takemura ,  Hiroshige Hirano ,  Yutaka Itoh ,  Hikari Sano ,  Masao Takahashi ,  Koji Koike

    IPC分类号： H01L23/52

    CPC分类号： H01L23/585 ,  H01L21/76832 ,  H01L23/522 ,  H01L23/53295 ,  H01L23/562 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device includes at least three or more wiring layers stacked in an interlayer insulating film on a semiconductor substrate, a seal ring provided at the outer periphery of a chip region of the semiconductor substrate and a chip strength reinforcement provided in part of the chip region near the seal ring. The chip strength reinforcement is made of a plurality of dummy wiring structures and each of the plurality of dummy wiring structures is formed to extend across and within two or more of the wiring layers including one or none of the bottommost wiring layer and the topmost wiring layer using a via portion.

    摘要翻译： 一种半导体器件包括在半导体衬底上的层间绝缘膜中堆叠的至少三个或更多个布线层，设置在半导体衬底的芯片区域的外周处的密封环和在芯片区域的一部分中提供的芯片强度增强 靠近密封圈。 芯片强度加强件由多个虚拟布线结构构成，并且多个虚设布线结构中的每一个形成为跨越两个或更多个布线层中的两个或更多个布线层，包括最下面的布线层和最上面的布线层 使用通孔部分。

    Semiconductor device
    10.
    发明申请
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US20070001308A1

    公开(公告)日：2007-01-04

    申请号：US11452957

    申请日：2006-06-15

    申请人： Koji Takemura ,  Hiroshige Hirano ,  Yutaka Itoh ,  Hikari Sano ,  Masao Takahashi ,  Koji Koike

    发明人： Koji Takemura ,  Hiroshige Hirano ,  Yutaka Itoh ,  Hikari Sano ,  Masao Takahashi ,  Koji Koike

    IPC分类号： H01L23/52 ,  H01L23/48

    CPC分类号： H01L23/585 ,  H01L21/76832 ,  H01L23/522 ,  H01L23/53295 ,  H01L23/562 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device includes at least three or more wiring layers stacked in an interlayer insulating film on a semiconductor substrate, a seal ring provided at the outer periphery of a chip region of the semiconductor substrate and a chip strength reinforcement provided in part of the chip region near the seal ring. The chip strength reinforcement is made of a plurality of dummy wiring structures and each of the plurality of dummy wiring structures is formed to extend across and within two or more of the wiring layers including one or none of the bottommost wiring layer and the topmost wiring layer using a via portion.

    摘要翻译： 一种半导体器件包括在半导体衬底上的层间绝缘膜中堆叠的至少三个或更多个布线层，设置在半导体衬底的芯片区域的外周处的密封环和在芯片区域的一部分中提供的芯片强度增强 靠近密封圈。 芯片强度加强件由多个虚拟布线结构构成，并且多个虚设布线结构中的每一个形成为跨越两个或更多个布线层中的两个或更多个布线层，包括最下面的布线层和最上面的布线层 使用通孔部分。