公开(公告)号：US07836755B2

公开(公告)日：2010-11-23

申请号：US11943753

申请日：2007-11-21

申请人： Hiromi Shimazu ,  Hiroyuki Ohta ,  Yohei Tanno ,  Mari Uchida ,  Naoto Saito

发明人： Hiromi Shimazu ,  Hiroyuki Ohta ,  Yohei Tanno ,  Mari Uchida ,  Naoto Saito

IPC分类号： G01N33/00 ,  G01N37/00 ,  G01N33/18 ,  G01N33/487

CPC分类号： G01N25/02 ,  G01N2203/0075 ,  G01N2203/0092

摘要： In a solidification sensor for measuring a solidification state of a liquid with a high degree of accuracy in real time, and for making the sensor small-sized with a reduced power consumption, the solidification sensor comprises a liquid absorbing portion formed of a liquid absorbable material, a substrate coupled to the liquid absorbing portion and a strain sensor for measuring strain exerted to the substrate due to a volumetric change upon solidification of a liquid absorbed in the liquid absorbing portion.

摘要翻译： 在用于以实时高精度测量液体的凝固状态的凝固传感器中，并且为了使传感器小型化而具有降低的功率消耗，凝固传感器包括由液体吸收材料形成的液体吸收部分 ，耦合到液体吸收部分的基板和用于测量由于吸收在液体吸收部分中的液体固化时的体积变化而测量施加到基板的应变传感器。

公开(公告)号：US20080121024A1

公开(公告)日：2008-05-29

申请号：US11943753

申请日：2007-11-21

申请人： Hiromi Shimazu ,  Hiroyuki Ohta ,  Yohei Tanno ,  Mari Uchida ,  Naoto Saito

发明人： Hiromi Shimazu ,  Hiroyuki Ohta ,  Yohei Tanno ,  Mari Uchida ,  Naoto Saito

IPC分类号： G01N37/00

CPC分类号： G01N25/02 ,  G01N2203/0075 ,  G01N2203/0092

摘要： In a solidification sensor for measuring a solidification state of a liquid with a high degree of accuracy in real time, and for making the sensor small-sized with a reduced power consumption, the solidification sensor comprises a liquid absorbing portion formed of a liquid absorbable material, a substrate coupled to the liquid absorbing portion and a strain sensor for measuring strain exerted to the substrate due to a volumetric change upon solidification of a liquid absorbed in the liquid absorbing portion.

摘要翻译： 在用于以实时高精度测量液体的凝固状态的凝固传感器中，并且为了使传感器小型化而具有降低的功率消耗，凝固传感器包括由液体吸收材料形成的液体吸收部分 ，耦合到液体吸收部分的基板和用于测量由于吸收在液体吸收部分中的液体固化时的体积变化而测量施加到基板的应变传感器。

公开(公告)号：US06554194B1

公开(公告)日：2003-04-29

申请号：US09391089

申请日：1999-09-16

申请人： Koji Sasaki ,  Naoto Saito ,  Hideo Miura ,  Hiroyuki Ohta ,  Kunio Matsumoto ,  Ryozo Yoshino

发明人： Koji Sasaki ,  Naoto Saito ,  Hideo Miura ,  Hiroyuki Ohta ,  Kunio Matsumoto ,  Ryozo Yoshino

IPC分类号： G06K1906

CPC分类号： G06K19/07728 ,  G06K19/077

摘要： An IC card has an IC chip and a circuit layer formed between layers of a base material that are adhered together by an adhesive. The IC card has a thickness of 0.25 to 0.76 mm and therefore the thickness of the IC chip needs to be about 0.2 mm, which requires grinding of the IC chip. In use, the IC card is subject to bending forces which apply a bending stress on the chip. In the process of grinding the IC chip, grinding flaws having sharp parts arise that reduce the bending strength of the chip. Also, during the dicing process of the wafer, chipping occurs that results in notches having sharp tip parts being formed in the chip. The grinding flaws that result from the grinding and the notches that result from the chipping are etched to remove their sharpness, which occurs at the tip part of the grinding flaw or the tip part of the notch. By rounding these sharp parts through the etching step, the bending strength of the IC chip increases and the durability of the IC card is ensured.

摘要翻译： IC卡具有通过粘合剂粘合在一起的基底材料层之间形成的IC芯片和电路层。 IC卡的厚度为0.25〜0.76mm，因此IC芯片的厚度需要为0.2mm左右，需要研磨IC芯片。 在使用中，IC卡受到在芯片上施加弯曲应力的弯曲力。 在研磨IC芯片的过程中，产生具有尖锐部分的研磨缺陷会降低芯片的弯曲强度。 此外，在晶片的切割处理期间，发生切屑，导致在芯片中形成具有尖锐尖端部分的凹口。 由研磨产生的磨削缺陷和由切屑引起的切口被蚀刻以去除其在磨削缺口的尖端部分或凹口的尖端部分发生的锋利度。 通过蚀刻步骤对这些尖锐部分进行四舍五入，IC芯片的弯曲强度增加，并且确保了IC卡的耐久性。

公开(公告)号：US08063445B2

公开(公告)日：2011-11-22

申请号：US12462909

申请日：2009-08-11

申请人： Shinjiro Kato ,  Naoto Saito

发明人： Shinjiro Kato ,  Naoto Saito

IPC分类号： H01L29/76 ,  H01L29/788

CPC分类号： H01L29/0847 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/7835

摘要： Provided is a semiconductor device which includes a metal oxide semiconductor (MOS) transistor having high driving performance and high withstanding voltage with a thick gate oxide film. In the local oxidation-of-silicon (LOCOS) offset MOS transistor having high withstanding voltage, in order to prevent a gate oxide film (6) formed on a channel formation region (7) from being etched at a time of removing the gate oxide film (6) with a polycrystalline silicon gate electrode (8) being used as a mask to form a second conductivity type high concentration source region (4) and a second conductivity type high concentration drain region (5), a source field oxide film (14) is formed also on a source side of the channel formation region (7), and in addition, a length of a second conductivity type high concentration source field region (13) is optimized. Accordingly, it is possible to obtain a MOS transistor having high driving performance and high withstanding voltage with a thick gate oxide film.

摘要翻译： 提供一种半导体器件，其包括具有高驱动性能的金属氧化物半导体（MOS）晶体管和具有较厚栅极氧化膜的高耐压。 在具有高耐受电压的局部氧化硅（LOCOS）偏移MOS晶体管中，为了防止形成在沟道形成区域（7）上的栅极氧化膜（6）在去除栅极氧化物时被蚀刻 使用多晶硅栅电极（8）作为掩模的膜（6）形成第二导电型高浓度源区（4）和第二导电型高浓度漏区（5），源场氧化膜 14）也形成在沟道形成区域（7）的源极侧，此外，第二导电型高浓度源极场区域（13）的长度被优化。 因此，可以通过厚栅极氧化膜获得具有高驱动性能和高耐受电压的MOS晶体管。

公开(公告)号：US20090152558A1

公开(公告)日：2009-06-18

申请号：US12315634

申请日：2008-12-04

申请人： Naoto Saito

发明人： Naoto Saito

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/66636 ,  H01L29/4236 ,  H01L29/66621 ,  H01L29/66787 ,  H01L29/7834

摘要： Provided is a lateral semiconductor device with a trench structure for improving driving capability. A trench portion is formed in a well to give concave and convex portions in a gate width direction. A gate electrode is formed inside and above the trench portion with an insulating film therebetween. A source region is formed on one side of the gate electrode in a gate length direction, and a drain region is formed on the other side, both formed by impurity diffusion from polycrystalline silicon containing an impurity and filling the inside of the trench portion, deep enough to reach vicinity of the bottom of the gate electrode (vicinity of bottom of trench portion). By thus forming a deep source region and a deep drain region, current flow that would otherwise concentrate on a shallow part in the gate electrode becomes uniform throughout the trench portion and widening of an effective gate width owing to the concave and convex portions formed in the well lowers ON resistance, improving the driving capability.

摘要翻译： 提供一种具有用于提高驱动能力的沟槽结构的横向半导体器件。 在阱中形成沟槽部，以在栅极宽度方向上形成凹部和凸部。 在沟槽部分的内部和上方形成栅电极，其间具有绝缘膜。 源极区域在栅极长度方向的一侧形成，另一侧形成漏极区域，二者均由含有杂质的多晶硅的杂质扩散形成，并填充沟槽部分的内部，深度 足以到达栅电极的底部附近（沟槽部分的底部附近）。 由此形成深源极区域和深漏极区域，否则将集中在栅极电极的浅部上的电流在整个沟槽部分变得均匀，并且由于在 良好的降低ON电阻，提高驾驶能力。

公开(公告)号：US5851909A

公开(公告)日：1998-12-22

申请号：US6152

申请日：1993-01-19

申请人： Masaaki Kamiya ,  Kenji Aoki ,  Naoto Saito

发明人： Masaaki Kamiya ,  Kenji Aoki ,  Naoto Saito

IPC分类号： H01L21/225 ,  H01L21/336 ,  H01L29/08 ,  H01L29/78

CPC分类号： H01L29/6659 ,  H01L21/2254 ,  H01L29/0847 ,  H01L29/78 ,  Y10S438/974

摘要： An impurity adsorption layer is formed on a substrate surface and solid-phase thermal diffusion is carried out to form source and drain regions for a metal-insulator-semiconductor field-effect-transistor having lightly doped drain structure or double doped drain structure. The thus formed impurity-doped region is ultrashallow, thereby producing high speed semiconductor devices of small dimensions.

摘要翻译： 在衬底表面上形成杂质吸附层，并进行固相热扩散以形成具有轻掺杂漏极结构或双掺杂漏极结构的金属 - 绝缘体 - 半导体场效应晶体管的源区和漏区。 这样形成的杂质掺杂区域是超浅的，从而制造尺寸小的高速半导体器件。

公开(公告)号：US5753530A

公开(公告)日：1998-05-19

申请号：US449655

申请日：1995-05-24

申请人： Tadao Akamine ,  Naoto Saito ,  Kenji Aoki ,  Yoshikazu Kojima

发明人： Tadao Akamine ,  Naoto Saito ,  Kenji Aoki ,  Yoshikazu Kojima

IPC分类号： H01L21/225 ,  H01L21/285 ,  H01L21/306 ,  H01L21/331 ,  H01L21/336 ,  H01L21/385

CPC分类号： H01L21/02046 ,  H01L21/2257 ,  H01L21/28512 ,  H01L29/66272 ,  H01L29/66545 ,  H01L29/66575 ,  Y10S438/906

摘要： A solid phase diffusion process using boron silicide film as diffusion source to improve controllability of diffusion of boron impurity into a silicon substrate in order to achieve a shallow junction. The process includes: cleaning the surface of a Si substrate by removing the native oxide film thereof to expose an active surface; treating the active surface to form thereon a boron silicide film as an impurity source; and introducing boron impurity from the boron silicide film into the Si substrate to form a boron diffusion layer. In this manner, a boron diffusion layer having a high surface concentration and a shallow junction can be formed because the boron silicide film is formed directly on the surface of the Si substrate. Because the boron silicide film is chemically and physically stable, an improved diffusion controllability is obtained. The diffusion controllability is further improved by accurately evaluating the impurity film optically during the fabrication process. A structure composed of a boron diffusion layer and a boron silicide region provides a high speed, highly integrated, and highly reliable semiconductor device, particularly when the boron silicide region is disposed between an impurity region and an electrode metal.

摘要翻译： 使用硅化硅膜作为扩散源的固相扩散工艺，以提高硼杂质扩散到硅衬底中的可控性，以便实现浅结。 该方法包括：通过去除其自然氧化膜以暴露活性表面来清洁Si衬底的表面; 处理活性表面以形成作为杂质源的硼化硅膜; 并将硼杂质从硅化硅膜引入Si衬底中以形成硼扩散层。 以这种方式，可以形成具有高表面浓度和浅结的硼扩散层，因为硅化硅膜直接形成在Si衬底的表面上。 因为硼化硅膜在化学和物理上是稳定的，所以获得改进的扩散控制性。 通过在制造过程中光学地精确评估杂质膜，进一步提高了扩散控制性。 由硼扩散层和硼硅化物区组成的结构提供高速，高度集成且高度可靠的半导体器件，特别是当硅化硼区域设置在杂质区域和电极金属之间时。

公开(公告)号：US5514620A

公开(公告)日：1996-05-07

申请号：US210769

申请日：1994-03-21

申请人： Kenji Aoki ,  Tadao Akamine ,  Naoto Saito

发明人： Kenji Aoki ,  Tadao Akamine ,  Naoto Saito

IPC分类号： H01L21/225 ,  H01L21/329 ,  H01L21/822 ,  H01L27/04 ,  H01L29/861 ,  H01L29/866 ,  H01L29/88 ,  H01L29/93 ,  H01L31/0248 ,  H01L31/103 ,  H01L31/18

CPC分类号： H01L29/66151 ,  H01L21/2254 ,  H01L29/66136 ,  H01L29/66174 ,  H01L31/103 ,  H01L31/1804 ,  Y02E10/547 ,  Y02P70/521 ,  Y10S438/906 ,  Y10S438/914

摘要： A PN junction device is formed by removing an inert film from a surface of an N type semiconductor layer to expose an active face, then applying a source gas containing an P type impurity component to the active face to form an impurity adsorption film, and thereafter carrying out a solid-phase diffusion of the impurity is carried out from a diffusion source composed of the P type impurity adsorption film into the N type semiconductor layer to form therein a P type semiconductor layer to thereby provide a PN junction. Lastly, a pair of electrodes are connected to the respective semiconductor layers to form the an PN junction device.

摘要翻译： 通过从N型半导体层的表面去除惰性膜以暴露活性面，然后将含有P型杂质成分的源气体施加到活性面上形成杂质吸附膜，形成PN结器件，之后 从由P型杂质吸附膜构成的扩散源向N型半导体层中进行杂质的固相扩散，形成P型半导体层，由此提供PN结。 最后，一对电极连接到各个半导体层以形成PN结器件。

公开(公告)号：US07714425B2

公开(公告)日：2010-05-11

申请号：US12233663

申请日：2008-09-19

申请人： Masahiro Yamaguchi ,  Hisashi Tanie ,  Naoto Saito

发明人： Masahiro Yamaguchi ,  Hisashi Tanie ,  Naoto Saito

IPC分类号： H01L23/02

CPC分类号： H01L25/0657 ,  H01L23/4985 ,  H01L24/50 ,  H01L25/105 ,  H01L2225/06572 ,  H01L2225/06579 ,  H01L2225/1023 ,  H01L2225/107

摘要： A semiconductor device includes a second semiconductor package, which includes a substrate and at least one semiconductor package. The substrate includes a terminal group formed on a surface thereof. At least one first semiconductor package is stacked on the substrate, and includes a plurality of flexible substrates, each of which includes a wiring group on a surface thereof and each of which is bending-deformable. At least one first semiconductor package includes a plurality of semiconductor elements mounted on a plurality of flexible substrates. Electric conduction through the second semiconductor package is established by connecting the wiring group on each of a plurality of flexible substrates to the terminal group on the substrate. Further, at least one terminal of the terminal group on the substrate is electrically connected to all of the plurality of semiconductor elements on at least one first semiconductor package, and at least one other terminal of the terminal group is electrically connected only to particular semiconductor elements of the plurality of semiconductor elements.

摘要翻译： 半导体器件包括第二半导体封装，其包括衬底和至少一个半导体封装。 基板包括在其表面上形成的端子组。 至少一个第一半导体封装堆叠在基板上，并且包括多个柔性基板，每个柔性基板在其表面上包括布线组，每个可弯曲变形。 至少一个第一半导体封装包括安装在多个柔性基板上的多个半导体元件。 通过将多个柔性基板中的每一个上的布线组连接到基板上的端子组来建立通过第二半导体封装的导电。 此外，衬底上的端子组的至少一个端子与至少一个第一半导体封装上的所有多个半导体元件电连接，并且端子组的至少一个其它端子仅电连接到特定的半导体元件 的多个半导体元件。

公开(公告)号：US06335256B1

公开(公告)日：2002-01-01

申请号：US09516985

申请日：2000-03-01

申请人： Naoto Saito

发明人： Naoto Saito

IPC分类号： H01L21331

CPC分类号： H01L29/66272 ,  H01L21/8249

摘要： There is provided a bipolar transistor integrated circuit device having excellent characteristics by a simple process. A region where an impurity is not introduced is disposed in a part of a buried layer region for separating a collector region from a substrate, so that a bipolar transistor having low collector resistance can be formed. This can be applied also to a BiCMOS where insulated field effect transistors exist on the same substrate. These processes can be realized without adding a number of steps to a conventional process.

摘要翻译： 提供一种通过简单的工艺具有优异特性的双极晶体管集成电路器件。 在用于从基板分离集电极区域的掩埋层区域的一部分中设置不引入杂质的区域，从而可以形成具有低集电极电阻的双极晶体管。 这也可以应用于同一衬底上存在绝缘场效应晶体管的BiCMOS。 可以实现这些过程，而不需要对常规方法添加多个步骤。