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    DUAL POLYSILICON GATE OF A SEMICONDUCTOR DEVICE WITH A MULTI-PLANE CHANNEL
    2.
    发明申请
    DUAL POLYSILICON GATE OF A SEMICONDUCTOR DEVICE WITH A MULTI-PLANE CHANNEL 失效
    具有多平面通道的半导体器件的双聚硅栅

    公开(公告)号：US20100084714A1

    公开(公告)日：2010-04-08

    申请号：US12632736

    申请日：2009-12-07

    申请人： Kwan-Yong LIM ,  Heung-Jae CHO ,  Min-Gyu SUNG

    发明人： Kwan-Yong LIM ,  Heung-Jae CHO ,  Min-Gyu SUNG

    IPC分类号： H01L27/092

    CPC分类号： H01L29/7831 ,  H01L21/2256 ,  H01L21/28035 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/82385 ,  H01L27/105 ,  H01L27/1052 ,  H01L29/66621 ,  H01L29/66795 ,  H01L29/7851

    摘要： A dual polysilicon gate of a semiconductor device includes a substrate having a first region, a second region, and a third region, a channel region with a recessed structure formed in the first region of the substrate, a gate insulating layer formed over the substrate, a first polysilicon layer filled into the channel region, and formed over the gate insulating layer of the first and second regions, a second polysilicon layer formed over the gate insulating layer of the third region, and an insulating layer doped with an impurity, and disposed inside the first polysilicon layer in the channel region.

    摘要翻译： 半导体器件的双多晶硅栅极包括具有第一区域，第二区域和第三区域的衬底，形成在衬底的第一区域中的凹陷结构的沟道区，在衬底上形成的栅极绝缘层， 并且形成在所述第一和第二区域的所述栅极绝缘层之上的第一多晶硅层，形成在所述第三区域的所述栅极绝缘层上的第二多晶硅层和掺杂有杂质的绝缘层， 在通道区域的第一多晶硅层的内部。

    SEMICONDUCTOR DEVICE WITH GATE STRUCTURE
    4.
    发明申请
    SEMICONDUCTOR DEVICE WITH GATE STRUCTURE 失效
    具有门结构的半导体器件

    公开(公告)号：US20110042760A1

    公开(公告)日：2011-02-24

    申请号：US12861679

    申请日：2010-08-23

    申请人： Min-Gyu SUNG ,  Hong-Seon YANG ,  Heung-Jae CHO ,  Yong-Soo KIM ,  Kwan-Yong LIM

    发明人： Min-Gyu SUNG ,  Hong-Seon YANG ,  Heung-Jae CHO ,  Yong-Soo KIM ,  Kwan-Yong LIM

    IPC分类号： H01L29/772

    CPC分类号： H01L21/28061 ,  H01L21/324 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/4941

    摘要： A gate structure of a semiconductor device includes an intermediate structure, wherein the intermediate structure includes a titanium layer and a tungsten silicide layer. A method for forming a gate structure of a semiconductor device includes forming a polysilicon-based electrode. An intermediate structure, which includes a titanium layer and a tungsten silicide layer, is formed over the polysilicon-based electrode. A metal electrode is formed over the intermediate structure.

    摘要翻译： 半导体器件的栅极结构包括中间结构，其中中间结构包括钛层和硅化钨层。 一种用于形成半导体器件的栅极结构的方法包括形成多晶硅基电极。 在多晶硅基电极上形成包括钛层和硅化钨层的中间结构。 在中间结构上形成金属电极。

    METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE WITH VERTICAL GATE TRANSISTOR
    7.
    发明申请
    METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE WITH VERTICAL GATE TRANSISTOR 失效
    用垂直栅极晶体管制造半导体器件的方法

    公开(公告)号：US20130109165A1

    公开(公告)日：2013-05-02

    申请号：US13338648

    申请日：2011-12-28

    申请人： Heung-Jae CHO

    发明人： Heung-Jae CHO

    IPC分类号： H01L21/28

    CPC分类号： H01L29/7827 ,  H01L21/31144 ,  H01L21/31155 ,  H01L21/32136 ,  H01L21/32137 ,  H01L29/66666

    摘要： A method for manufacturing a semiconductor device includes forming a plurality of pillars by etching a semiconductor substrate, forming a gate dielectric layer on sidewalls of the pillars and on surfaces of the semiconductor substrate between the pillars, forming an implant damage in a portion of the gate dielectric layer between two pillars by implanting ions into the portion of the gate dielectric layer, forming vertical gates to cover the sidewalls of the pillars, and removing the implant damage.

    摘要翻译： 一种用于制造半导体器件的方法包括通过蚀刻半导体衬底形成多个柱，在柱的侧壁上形成栅介质层，并在该柱之间的半导体衬底表面上形成栅极的一部分中的植入物损伤 通过将离子注入到栅极电介质层的部分中，形成两个柱之间的介电层，形成垂直栅极以覆盖柱的侧壁，以及去除植入物损伤。

    NONVOLATILE MEMORY DEVICE WITH MULTIPLE BLOCKING LAYERS AND METHOD OF FABRICATING THE SAME
    8.
    发明申请
    NONVOLATILE MEMORY DEVICE WITH MULTIPLE BLOCKING LAYERS AND METHOD OF FABRICATING THE SAME 有权
    具有多个阻挡层的非易失性存储器件及其制造方法

    公开(公告)号：US20110165769A1

    公开(公告)日：2011-07-07

    申请号：US13047258

    申请日：2011-03-14

    申请人： Heung-Jae CHO ,  Moon-Sig Joo ,  Yong-Soo Kim ,  Won-Joon Choi

    发明人： Heung-Jae CHO ,  Moon-Sig Joo ,  Yong-Soo Kim ,  Won-Joon Choi

    IPC分类号： H01L21/28

    CPC分类号： H01L21/28282 ,  H01L21/28273

    摘要： A nonvolatile memory device with a blocking layer controlling the transfer of electric charges in a charge storage layer includes the blocking layer having a first blocking layer in contact with the charge storage layer and a second blocking layer over the first blocking layer, wherein the first blocking layer has a greater energy band gap than the second blocking layer and the second blocking layer has a greater permittivity than the first blocking layer.

    摘要翻译： 具有控制电荷存储层中的电荷转移的阻挡层的非易失性存储器件包括具有与电荷存储层接触的第一阻挡层和第一阻挡层上的第二阻挡层的阻挡层，其中第一阻塞 层具有比第二阻挡层更大的能带隙，并且第二阻挡层具有比第一阻挡层更大的介电常数。